component
HEF40106BTT-Q100J
Public Made by Adomby adom
Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHEF40106BTT-Q100J
Nexperia · Inverters · TSSOP-14
HEF40106BTT-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Schmitt-trigger input of inverter 1; inputs include clamp diodes so current-limiting resistors can interface inputs above VDD, with input voltage recommended between VSS and VDD and input clamping current limited to ±10 mA. |
| 2 | 1Y | output | Inverted output of gate 1 (1Y = NOT 1A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 3 | 2A | input | Schmitt-trigger input of inverter 2; input voltage recommended between VSS and VDD, with input clamping current limited to ±10 mA. |
| 4 | 2Y | output | Inverted output of gate 2 (2Y = NOT 2A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 5 | 3A | input | Schmitt-trigger input of inverter 3; input voltage recommended between VSS and VDD, with input clamping current limited to ±10 mA. |
| 6 | 3Y | output | Inverted output of gate 3 (3Y = NOT 3A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 7 | VSS | power_in | Ground reference, 0 V; all voltages are referenced to this pin. |
| 8 | 4Y | output | Inverted output of gate 4 (4Y = NOT 4A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 9 | 4A | input | Schmitt-trigger input of inverter 4; input voltage recommended between VSS and VDD, with input clamping current limited to ±10 mA. |
| 10 | 5Y | output | Inverted output of gate 5 (5Y = NOT 5A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 11 | 5A | input | Schmitt-trigger input of inverter 5; input voltage recommended between VSS and VDD, with input clamping current limited to ±10 mA. |
| 12 | 6Y | output | Inverted output of gate 6 (6Y = NOT 6A); output clamping current limited to ±10 mA when the output is below VSS − 0.5 V or above VDD + 0.5 V. |
| 13 | 6A | input | Schmitt-trigger input of inverter 6; input voltage recommended between VSS and VDD, with input clamping current limited to ±10 mA. |
| 14 | VDD | power_in | Positive supply voltage, 3 V to 15 V recommended (absolute maximum 18 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 3 | 15 | V | 3 | ||
| Input voltage | VI | 0 | V | 3 | |||
| Ambient temperature in free air | Tamb | -40 | 125 | °C | in free air | 3 | |
| Supply voltage | VDD | -0.5 | 18 | V | 3 | ||
| Input clamping current | IIK | -10 | 10 | mA | VI < -0.5 V or VI > VDD + 0.5 V | 3 | |
| Input voltage | VI | -0.5 | V | 3 | |||
| Output clamping current | IOK | -10 | 10 | mA | VO < -0.5 V or VO > VDD + 0.5 V | 3 | |
| Input/output current | II/O | -10 | 10 | mA | 3 | ||
| Supply current | IDD | 50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Ambient temperature | Tamb | -40 | 125 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C [1] | 3 | ||
| Power dissipation per output | P | 100 | mW | 3 | |||
| HIGH-level output voltage | VOH | 4.95 | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 9.95 | V | /IO/ < 1 μA; VDD = 10 V; Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 14.95 | V | /IO/ < 1 μA; VDD = 15 V; Tamb = -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.05 | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level output current | IOH | -1.7 | mA | VO = 2.5 V; VDD = 5 V; Tamb = -40 °C | 4 | ||
| HIGH-level output current | IOH | -1.1 | mA | VO = 2.5 V; VDD = 5 V; Tamb = +125 °C | 4 | ||
| HIGH-level output current | IOH | -0.64 | mA | VO = 4.6 V; VDD = 5 V; Tamb = -40 °C | 4 | ||
| HIGH-level output current | IOH | -0.36 | mA | VO = 4.6 V; VDD = 5 V; Tamb = +125 °C | 4 | ||
| HIGH-level output current | IOH | -1.6 | mA | VO = 9.5 V; VDD = 10 V; Tamb = -40 °C | 4 | ||
| HIGH-level output current | IOH | -0.9 | mA | VO = 9.5 V; VDD = 10 V; Tamb = +125 °C | 4 | ||
| HIGH-level output current | IOH | -4.2 | mA | VO = 13.5 V; VDD = 15 V; Tamb = -40 °C | 4 | ||
| HIGH-level output current | IOH | -2.4 | mA | VO = 13.5 V; VDD = 15 V; Tamb = +125 °C | 4 | ||
| LOW-level output current | IOL | 0.64 | mA | VO = 0.4 V; VDD = 5 V; Tamb = -40 °C | 4 | ||
| LOW-level output current | IOL | 0.36 | mA | VO = 0.4 V; VDD = 5 V; Tamb = +125 °C | 4 | ||
| LOW-level output current | IOL | 1.6 | mA | VO = 0.5 V; VDD = 10 V; Tamb = -40 °C | 4 | ||
| LOW-level output current | IOL | 0.9 | mA | VO = 0.5 V; VDD = 10 V; Tamb = +125 °C | 4 | ||
| LOW-level output current | IOL | 4.2 | mA | VO = 1.5 V; VDD = 15 V; Tamb = -40 °C | 4 | ||
| LOW-level output current | IOL | 2.4 | mA | VO = 1.5 V; VDD = 15 V; Tamb = +125 °C | 4 | ||
| Input leakage current | II | -0.1 | 0.1 | μA | VDD = 15 V; Tamb = -40 °C | 4 | |
| Input leakage current | II | -1 | 1 | μA | VDD = 15 V; Tamb = +125 °C | 4 | |
| Supply current | IDD | 0.25 | μA | all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = -40 °C | 4 | ||
| Supply current | IDD | 7.5 | μA | all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = +125 °C | 4 | ||
| Supply current | IDD | 0.5 | μA | all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = -40 °C | 4 | ||
| Supply current | IDD | 15 | μA | all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = +125 °C | 4 | ||
| Supply current | IDD | 1 | μA | all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = -40 °C | 4 | ||
| Supply current | IDD | 30 | μA | all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = +125 °C | 4 | ||
| Input capacitance | CI | 7.5 | pF | Tamb = +25 °C | 4 | ||
| Positive-going threshold voltage | VT+ | 2 | 3 | 3.5 | V | VDD = 5 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| Positive-going threshold voltage | VT+ | 3.7 | 5.8 | 7 | V | VDD = 10 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| Positive-going threshold voltage | VT+ | 4.9 | 8.3 | 11 | V | VDD = 15 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| Negative-going threshold voltage | VT- | 1.5 | 2.2 | 3 | V | VDD = 5 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| Negative-going threshold voltage | VT- | 3 | 4.5 | 6.3 | V | VDD = 10 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| Negative-going threshold voltage | VT- | 4 | 6.5 | 10.1 | V | VDD = 15 V; Tamb = -40 °C to +125 °C (typ at Tamb = 25 °C) | 7 |
| HIGH to LOW propagation delay nA to nY | tPHL | 90 | 180 | ns | VDD = 5 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| HIGH to LOW propagation delay nA to nY | tPHL | 35 | 70 | ns | VDD = 10 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| HIGH to LOW propagation delay nA to nY | tPHL | 30 | 60 | ns | VDD = 15 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 75 | 150 | ns | VDD = 5 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 35 | 70 | ns | VDD = 10 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 30 | 60 | ns | VDD = 15 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| HIGH to LOW output transition time | tTHL | 60 | 120 | ns | VDD = 5 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| HIGH to LOW output transition time | tTHL | 30 | 60 | ns | VDD = 10 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| HIGH to LOW output transition time | tTHL | 20 | 40 | ns | VDD = 15 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH output transition time | tTLH | 60 | 120 | ns | VDD = 5 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH output transition time | tTLH | 30 | 60 | ns | VDD = 10 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 | |
| LOW to HIGH output transition time | tTLH | 20 | 40 | ns | VDD = 15 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C | 5 |
CAD (KiCad official)
- Symbol:
HEF40106BTT-Q100J - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
hef40106btt-q100j-etched.step/hef40106btt-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hef40106btt-q100j.step/hef40106btt-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
e43d69780be39c35, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).