# HEF40106BT-Q100J

**Nexperia** · Inverters · SOIC-14

HEF40106BT-Q100J from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Schmitt-trigger input of inverter 1; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 2 | 1Y | output | Inverted output of gate 1 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 3 | 2A | input | Schmitt-trigger input of inverter 2; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 4 | 2Y | output | Inverted output of gate 2 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 5 | 3A | input | Schmitt-trigger input of inverter 3; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 6 | 3Y | output | Inverted output of gate 3 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 7 | VSS | power_in | Ground reference (0 V); all voltages in the datasheet are referenced to VSS. |
| 8 | 4Y | output | Inverted output of gate 4 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 9 | 4A | input | Schmitt-trigger input of inverter 4; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 10 | 5Y | output | Inverted output of gate 5 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 11 | 5A | input | Schmitt-trigger input of inverter 5; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 12 | 6Y | output | Inverted output of gate 6 (Y = NOT A), with output clamping current limited to ±10 mA when VO < -0.5 V or VO > VDD + 0.5 V. |
| 13 | 6A | input | Schmitt-trigger input of inverter 6; clamp diodes allow current-limited drive above VDD, with input clamping current limited to ±10 mA when VI < -0.5 V or VI > VDD + 0.5 V. |
| 14 | VDD | power_in | Positive supply; recommended VDD is 3 V to 15 V (absolute maximum -0.5 V to +18 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VDD | -0.5 |  | 18 | V |  | 3 |
| input voltage | VI | -0.5 |  |  | V |  | 3 |
| input clamping current | IIK | -10 |  | 10 | mA | VI < -0.5 V or VI > VDD + 0.5 V | 3 |
| output clamping current | IOK | -10 |  | 10 | mA | VO < -0.5 V or VO > VDD + 0.5 V | 3 |
| input/output current | II/O | -10 |  | 10 | mA |  | 3 |
| supply current | IDD |  |  | 50 | mA |  | 3 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| supply voltage | VDD | 3 |  | 15 | V |  | 3 |
| input voltage | VI | 0 |  |  | V |  | 3 |
| ambient temperature | Tamb | -40 |  | 125 | °C | in free air | 3 |
| positive-going threshold voltage | VT+ | 2 | 3 | 3.5 | V | VDD = 5 V; Tamb = -40 °C to +125 °C | 7 |
| positive-going threshold voltage | VT+ | 3.7 | 5.8 | 7 | V | VDD = 10 V; Tamb = -40 °C to +125 °C | 7 |
| positive-going threshold voltage | VT+ | 4.9 | 8.3 | 11 | V | VDD = 15 V; Tamb = -40 °C to +125 °C | 7 |
| negative-going threshold voltage | VT- | 1.5 | 2.2 | 3 | V | VDD = 5 V; Tamb = -40 °C to +125 °C | 7 |
| negative-going threshold voltage | VT- | 3 | 4.5 | 6.3 | V | VDD = 10 V; Tamb = -40 °C to +125 °C | 7 |
| negative-going threshold voltage | VT- | 4 | 6.5 | 10.1 | V | VDD = 15 V; Tamb = -40 °C to +125 °C | 7 |
| hysteresis voltage | VH | 0.5 | 0.8 |  | V | VDD = 5 V; Tamb = -40 °C to +125 °C | 7 |
| hysteresis voltage | VH | 0.7 | 1.3 |  | V | VDD = 10 V; Tamb = -40 °C to +125 °C | 7 |
| hysteresis voltage | VH | 0.9 | 1.8 |  | V | VDD = 15 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH to LOW propagation delay nA to nY | tPHL |  | 90 | 180 | ns | VDD = 5 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH to LOW propagation delay nA to nY | tPHL |  | 35 | 70 | ns | VDD = 10 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH to LOW propagation delay nA to nY | tPHL |  | 30 | 60 | ns | VDD = 15 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH propagation delay nA to nY | tPLH |  | 75 | 150 | ns | VDD = 5 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH propagation delay nA to nY | tPLH |  | 35 | 70 | ns | VDD = 10 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH propagation delay nA to nY | tPLH |  | 30 | 60 | ns | VDD = 15 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH to LOW output transition time nY to LOW | tTHL |  | 60 | 120 | ns | VDD = 5 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH to LOW output transition time nY to LOW | tTHL |  | 30 | 60 | ns | VDD = 10 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH to LOW output transition time nY to LOW | tTHL |  | 20 | 40 | ns | VDD = 15 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH output transition time nY to HIGH | tTLH |  | 60 | 120 | ns | VDD = 5 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH output transition time nY to HIGH | tTLH |  | 30 | 60 | ns | VDD = 10 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| LOW to HIGH output transition time nY to HIGH | tTLH |  | 20 | 40 | ns | VDD = 15 V; Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns | 5 |
| HIGH-level output voltage | VOH | 4.95 |  |  | V | VDD = 5 V; /IO/ < 1 μA; Tamb = -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 9.95 |  |  | V | VDD = 10 V; /IO/ < 1 μA; Tamb = -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 14.95 |  |  | V | VDD = 15 V; /IO/ < 1 μA; Tamb = -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL |  |  | 0.05 | V | VDD = 5 V; /IO/ < 1 μA; Tamb = -40 °C to +125 °C | 4 |
| input capacitance | CI |  |  | 7.5 | pF | Tamb = +25 °C | 4 |
| HIGH-level output current | IOH |  |  | -1.7 | mA | VDD = 5 V; VO = 2.5 V; Tamb = -40 °C | 4 |
| HIGH-level output current | IOH |  |  | -1.1 | mA | VDD = 5 V; VO = 2.5 V; Tamb = +125 °C | 4 |
| HIGH-level output current | IOH |  |  | -0.64 | mA | VDD = 5 V; VO = 4.6 V; Tamb = -40 °C | 4 |
| HIGH-level output current | IOH |  |  | -0.36 | mA | VDD = 5 V; VO = 4.6 V; Tamb = +125 °C | 4 |
| HIGH-level output current | IOH |  |  | -1.6 | mA | VDD = 10 V; VO = 9.5 V; Tamb = -40 °C | 4 |
| HIGH-level output current | IOH |  |  | -0.9 | mA | VDD = 10 V; VO = 9.5 V; Tamb = +125 °C | 4 |
| HIGH-level output current | IOH |  |  | -4.2 | mA | VDD = 15 V; VO = 13.5 V; Tamb = -40 °C | 4 |
| HIGH-level output current | IOH |  |  | -2.4 | mA | VDD = 15 V; VO = 13.5 V; Tamb = +125 °C | 4 |
| LOW-level output current | IOL | 0.64 |  |  | mA | VDD = 5 V; VO = 0.4 V; Tamb = -40 °C | 4 |
| LOW-level output current | IOL | 0.36 |  |  | mA | VDD = 5 V; VO = 0.4 V; Tamb = +125 °C | 4 |
| LOW-level output current | IOL | 1.6 |  |  | mA | VDD = 10 V; VO = 0.5 V; Tamb = -40 °C | 4 |
| LOW-level output current | IOL | 0.9 |  |  | mA | VDD = 10 V; VO = 0.5 V; Tamb = +125 °C | 4 |
| LOW-level output current | IOL | 4.2 |  |  | mA | VDD = 15 V; VO = 1.5 V; Tamb = -40 °C | 4 |
| LOW-level output current | IOL | 2.4 |  |  | mA | VDD = 15 V; VO = 1.5 V; Tamb = +125 °C | 4 |
| supply current | IDD |  |  | 0.25 | μA | VDD = 5 V; all valid input combinations; IO = 0 A; Tamb = -40 °C | 4 |
| supply current | IDD |  |  | 7.5 | μA | VDD = 5 V; all valid input combinations; IO = 0 A; Tamb = +125 °C | 4 |
| supply current | IDD |  |  | 0.5 | μA | VDD = 10 V; all valid input combinations; IO = 0 A; Tamb = -40 °C | 4 |
| supply current | IDD |  |  | 15 | μA | VDD = 10 V; all valid input combinations; IO = 0 A; Tamb = +125 °C | 4 |
| supply current | IDD |  |  | 1 | μA | VDD = 15 V; all valid input combinations; IO = 0 A; Tamb = -40 °C | 4 |
| supply current | IDD |  |  | 30 | μA | VDD = 15 V; all valid input combinations; IO = 0 A; Tamb = +125 °C | 4 |
| input leakage current | II | -0.1 |  | 0.1 | μA | VDD = 15 V; Tamb = -40 °C | 4 |
| input leakage current | II | -1 |  | 1 | μA | VDD = 15 V; Tamb = +125 °C | 4 |

## CAD (KiCad official)

- Symbol: `HEF40106BT-Q100J`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `hef40106bt-q100j-etched.step` / `hef40106bt-q100j-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hef40106bt-q100j.step` / `hef40106bt-q100j.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884926830170112) (14 pp, sha256 `e43d69780be39c35`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hef40106bt-q100j-datasheet.pdf)