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HD3SS215IRTQR

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Texas Instruments Interface - Specialized, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icshd3ss215irtqrfactory-2.0.0extractor-text

Verified HD3SS215IRTQR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 57 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: HD3SS215IRTQR · QFN-56-EP(8x8) · 57 pins
  • ✓copper: 57 copper pads, none touching another net
  • ✓datasheet: all 57 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C2674393, digikey 296-42982-2-ND, mouser 595-HD3SS215IRTQR
  • ✓family: QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-97mpxp5u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 57 pins = 57 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 57 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ hd3ss215irtqr.kicad_sym✓ hd3ss215irtqr.kicad_mod✓ hd3ss215irtqr.step
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HD3SS215IRTQR

Texas Instruments · Interface - Specialized · QFN-56-EP(8x8)

HD3SS215IRTQR from Texas Instruments, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AUX_SEL input Three-level AUX/DDC selection control pin used together with Dx_SEL to route AUX and DDC channels.
2 DC0(P) bidirectional Port C, Channel 0 high-speed positive signal; the switch supports data rates up to 6 Gbps.
3 DC0(N) bidirectional Port C, Channel 0 high-speed negative signal; the switch supports data rates up to 6 Gbps.
4 GND power_in Ground pin.
5 DC1(P) bidirectional Port C, Channel 1 high-speed positive signal; the switch supports data rates up to 6 Gbps.
6 DC1(N) bidirectional Port C, Channel 1 high-speed negative signal; the switch supports data rates up to 6 Gbps.
7 GND power_in Ground pin.
8 DC2(P) bidirectional Port C, Channel 2 high-speed positive signal; the switch supports data rates up to 6 Gbps.
9 DC2(N) bidirectional Port C, Channel 2 high-speed negative signal; the switch supports data rates up to 6 Gbps.
10 GND power_in Ground pin.
11 DC3(P) bidirectional Port C, Channel 3 high-speed positive signal; the switch supports data rates up to 6 Gbps.
12 DC3(N) bidirectional Port C, Channel 3 high-speed negative signal; the switch supports data rates up to 6 Gbps.
13 AUXC(P) bidirectional Port C AUX positive signal for DisplayPort auxiliary channel switching.
14 AUXC(N) bidirectional Port C AUX negative signal for DisplayPort auxiliary channel switching.
15 HPDC bidirectional Port C hot plug detect signal, switched between the source and sink ports.
16 HPDA bidirectional Port A hot plug detect signal, switched between the source and sink ports.
17 HPDB bidirectional Port B hot plug detect signal, switched between the source and sink ports.
18 DDCCLK_C bidirectional Port C DDC clock signal; absolute maximum rating is -0.5 V to 6 V.
19 VDD power_in 3.3 V positive power supply, recommended range 3 V to 3.6 V.
20 NC unconnected Not connected.
21 NC unconnected Not connected.
22 DDCCLK_B bidirectional Port B DDC clock signal; absolute maximum rating is -0.5 V to 6 V.
23 DDCDAT_B bidirectional Port B DDC data signal; absolute maximum rating is -0.5 V to 6 V.
24 AUXB(P) bidirectional Port B AUX positive signal for DisplayPort auxiliary channel switching.
25 AUXB(N) bidirectional Port B AUX negative signal for DisplayPort auxiliary channel switching.
26 DDCDAT_C bidirectional Port C DDC data signal; absolute maximum rating is -0.5 V to 6 V.
27 DDCCLK_A bidirectional Port A DDC clock signal; absolute maximum rating is -0.5 V to 6 V.
28 DDCDAT_A bidirectional Port A DDC data signal; absolute maximum rating is -0.5 V to 6 V.
29 AUXA(N) bidirectional Port A AUX negative signal for DisplayPort auxiliary channel switching.
30 AUXA(P) bidirectional Port A AUX positive signal for DisplayPort auxiliary channel switching.
31 DB3(N) bidirectional Port B, Channel 3 high-speed negative signal; the switch supports data rates up to 6 Gbps.
32 DB3(P) bidirectional Port B, Channel 3 high-speed positive signal; the switch supports data rates up to 6 Gbps.
33 GND power_in Ground pin.
34 DB2(N) bidirectional Port B, Channel 2 high-speed negative signal; the switch supports data rates up to 6 Gbps.
35 DB2(P) bidirectional Port B, Channel 2 high-speed positive signal; the switch supports data rates up to 6 Gbps.
36 GND power_in Ground pin.
37 DB1(N) bidirectional Port B, Channel 1 high-speed negative signal; the switch supports data rates up to 6 Gbps.
38 DB1(P) bidirectional Port B, Channel 1 high-speed positive signal; the switch supports data rates up to 6 Gbps.
39 GND power_in Ground pin.
40 DB0(N) bidirectional Port B, Channel 0 high-speed negative signal; the switch supports data rates up to 6 Gbps.
41 DB0(P) bidirectional Port B, Channel 0 high-speed positive signal; the switch supports data rates up to 6 Gbps.
42 NC unconnected Not connected.
43 OE input Output enable: OE high is normal operation and OE low places the device in standby mode to save power.
44 DA3(N) bidirectional Port A, Channel 3 high-speed negative signal; the switch supports data rates up to 6 Gbps.
45 DA3(P) bidirectional Port A, Channel 3 high-speed positive signal; the switch supports data rates up to 6 Gbps.
46 GND power_in Ground pin.
47 DA2(N) bidirectional Port A, Channel 2 high-speed negative signal; the switch supports data rates up to 6 Gbps.
48 DA2(P) bidirectional Port A, Channel 2 high-speed positive signal; the switch supports data rates up to 6 Gbps.
49 GND power_in Ground pin.
50 DA1(N) bidirectional Port A, Channel 1 high-speed negative signal; the switch supports data rates up to 6 Gbps.
51 DA1(P) bidirectional Port A, Channel 1 high-speed positive signal; the switch supports data rates up to 6 Gbps.
52 GND power_in Ground pin.
53 DA0(N) bidirectional Port A, Channel 0 high-speed negative signal; the switch supports data rates up to 6 Gbps.
54 DA0(P) bidirectional Port A, Channel 0 high-speed positive signal; the switch supports data rates up to 6 Gbps.
55 VDD power_in 3.3 V positive power supply, recommended range 3 V to 3.6 V.
56 Dx_SEL input Three-level high-speed port selection control pin that selects the active port.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-56-EP(8x8)
Category Interface ICs
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (abs max) VDD -0.5 4 V 7
Differential I/O voltage (abs max) -0.5 4 V Differential I/O 7
AUX_SEL, Dx_SEL voltage (abs max) -0.5 4 V AUX_SEL, Dx_SEL 7
HPDx, DDCCLK_X, DDCDAT_X voltage (abs max) -0.5 6 V HPDx, DDCCLK_X, DDCDAT_X 7
Storage temperature Tstg -65 150 °C 7
ESD HBM V(ESD) -1500 1500 V Human body model, ANSI/ESDA/JEDEC JS-001, all pins 7
ESD CDM V(ESD) -1250 1250 V Charged device model, JESD22-C101, all pins 7
Main power supply VDD 3 3.3 3.6 V 7
Operating free-air temperature HD3SS215I TA -40 85 °C HD3SS215I 7
AC coupling capacitor CAC 75 100 200 nF 7
Junction-to-ambient thermal resistance RθJA 90.5 °C/W RTQ (56 pin) 7
Junction-to-case (top) thermal resistance RθJC(top) 41.9 °C/W RTQ (56 pin) 7
Junction-to-board thermal resistance RθJB 53.9 °C/W RTQ (56 pin) 7
Junction-to-top characterization parameter ψJT 1.8 °C/W RTQ (56 pin) 7
Junction-to-board characterization parameter ψJB 53.4 °C/W RTQ (56 pin) 7
Supply voltage VDD 3 3.3 3.6 V 8
Input high voltage, control pins VIH 2 V Control Pins, Signal Pins (Dx_SEL, AUX_SEL, OE); max VDD 8
Input high voltage, HPD and DDC VIH 2 5.5 V HPD and DDC 8
Input low voltage VIL -0.1 0.8 V Control Pins, Signal Pins (Dx_SEL, AUX_SEL, OE) 8
Differential voltage VI/O_Diff 0 1.8 Vpp Switch I/O diff voltage 8
Common voltage VCM 0 3.3 V Switch common mode voltage 8
Input high current IIH 1 µA VDD = 3.6 V, VIN = VDD 8
Input mid current IIM 1 µA VDD = 3.6 V, VIN = VDD/2 8
Input low current IIL 0.01 1 µA VDD = 3.6 V, VIN = GND 8
Leakage current Dx_SEL, AUX_SEL (OE high) ILK 0.01 2 µA VDD = 3.6 V, VIN = 2 V, OE = 3.3 V 8
Leakage current Dx_SEL, AUX_SEL (OE low) ILK 0.01 2 µA VDD = 3.6 V, VIN = 2 V, OE = 0 V 8
Leakage current HPDx/DDCx ILK 0.01 5 µA VDD = 3.6 V, VIN = 2 V, OE = 0 V; Dx_SEL = 3.3 V 8
Device shut down current IOFF 8 µA VDD = 3.6 V, OE = GND 8
Supply current IDD 2.5 3.2 mA VDD = 3.6 V, Dx_SEL= VDD; AUX_SEL = GND; Outputs Floating 8
ON resistance (high speed) RON 8 14 Ω VCM = 0 V-3.3 V, IO = -1mA 8
On resistance match ΔRON 1.5 Ω VCM = 0 V-3. 3V, IO = -1 mA 8
On resistance flatness RFLAT_ON 1.3 Ω VCM = 0 V-3.3 V 8
ON resistance on AUX channel RON(AUX) 5 8 Ω VCM = 0 V-3.3 V, IO = -8 mA 8
ON resistance on DDC channel RON(DDC) 30 40 Ω VCM = 0.4 V, IO = -3 mA 8
Switch propagation delay tPD 200 ps RSC and RLOAD = 50 Ω, See Figure 2 9
Time from OE high to valid data ton(OE_L-H) 1 2 µs RSC and RLOAD = 50 Ω, VCM = 3 V - 3.3 V 9
Time from OE low to Z-state toff(OE_H-L) 15 50 µs RSC and RLOAD = 50 Ω, VCM = 3 V - 3.3 V 9
Port switch-over time tSWITCH_OVER 0.7 1 µs RSC and RLOAD = 50 Ω, See Figure 1 9
Dx_SEL/AUX_SEL-to-Switch ton (HPD) ton 0.7 1 µs RLOAD = 125k Ω, See Figure 1 9
Dx_SEL/AUX_SEL-to-Switch toff (HPD) toff 0.7 20 µs RLOAD = 125k Ω, See Figure 1 9
Inter-pair output skew tSK(O) 30 ps RSC and RLOAD = 50 Ω, See Figure 2 9
Intra-pair output skew tSK(b-b) 1 5 ps RSC and RLOAD = 50 Ω, See Figure 2 9
Differential return loss 1.35 GHz RL -17 dB RTQ package, 1.35 GHz 9
Differential return loss 3 GHz RL -13 dB RTQ package, 3 GHz 9
Differential crosstalk XTALK -35 dB RTQ package, 2.7 GHz 9
Differential off-isolation OIRR -16 dB RTQ package, 3 GHz 9
Differential insertion loss 1.35 GHz IL -2 dB RTQ package, f = 1.35 GHz 9
Differential insertion loss 3 GHz IL -2.4 dB RTQ package, f = 3 GHz 9
Differential -3-dB bandwidth BWDx 5 GHz RTQ package 9
AUX -3-dB bandwidth BWAUX 720 MHz 9

CAD (KiCad official)

  • Symbol: HD3SS215IRTQR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: hd3ss215irtqr-etched.step / hd3ss215irtqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hd3ss215irtqr.step / hd3ss215irtqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 e0d86e6316704cbf, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF