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HCPL0601R2

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onsemi Logic Output Optoisolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HCPL0601R2

onsemi · Logic Output Optoisolators · SOIC-8

HCPL0601R2 from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Marked N/C (no connection) in the single-channel circuit drawing, so it is left unconnected.
2 VF (anode) input LED anode input; the input threshold current IFT is 5 mA max and the high-level input current IFH is 6.3 to 15 mA, with 6.3 mA guard-banded to allow at least 20% CTR degradation.
3 VF (cathode) passive LED cathode (input return); reverse input voltage VR is limited to 5.0 V max and DC forward input current to 50 mA max for a single-channel device.
4 NC unconnected Marked N/C (no connection) in the single-channel circuit drawing, so it is left unconnected.
5 GND power_in Ground reference for the detector; a 0.1 µF bypass capacitor must be connected between pins 8 and 5, as close to the package as possible.
6 VO output Open-collector logic gate output (wired-OR capable) that requires an external pull-up of 330 Ω to 4 kΩ; output current is limited to 50 mA max and output voltage to 7.0 V max per channel.
7 VE input Enable input with an internal pull-up resistor (no external pull-up needed); VEL must stay at or below 0.8 V for disable and VEH at or above 2.0 V for enable, and it must not exceed VCC by more than 500 mV.
8 VCC power_in Detector supply, 4.5 V to 5.5 V recommended operating range with 7.0 V max for 1 minute; decouple with a 0.1 µF capacitor to pin 5.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Optoisolators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Current, Low Level IFL 0 250 µA 4
Input Current, High Level IFH 6.3 15 mA *guard-banded value; allows at least 20% CTR degradation 4
Supply Voltage, Output VCC 4.5 5.5 V 4
Enable Voltage, Low Level VEL 0 0.8 V Single channel only 4
Enable Voltage, High Level VEH 2 V Single channel only; max printed as VCC 4
Operating Temperature TA -40 85 °C 4
Output Pull-up RL 330 Ω Max printed as 4K Ω; not converted 4
Storage Temperature TSTG -40 125 °C 4
Operating Temperature TOPR -40 85 °C No derating required up to 85°C 4
DC/Average Forward Input Current (each channel) IF 50 mA Single channel 4
Enable Input Voltage VE 5.5 V Single channel; not to exceed VCC by more than 500mV 4
Reverse Input Voltage (each channel) VR 5 V 4
Power Dissipation PI 45 mW Single channel 4
Supply Voltage VCC 7 V 1 minute max 4
Output Current (each channel) IO 50 mA Single channel 4
Output Voltage (each channel) VO 7 V 4
Collector Output Power Dissipation PO 85 mW Single channel 4
Input Forward Voltage VF 1.8 V IF = 10mA 5
Input Reverse Breakdown Voltage BVR 5 V IR = 10µA 5
High Level Supply Current ICCH 10 mA IF = 0mA, VE = 0.5 V, VCC = 5.5V; single channel 5
Low Level Supply Current ICCL 13 mA IF = 10mA, VE = 0.5 V, VCC = 5.5V; single channel 5
Low Level Enable Current IEL -1.6 mA VCC = 5.5V, VE = 0.5V; single channel 5
High Level Enable Current IEH -1.6 mA VCC = 5.5V, VE = 2.0V; single channel 5
High Level Enable Voltage VEH 2 V VCC = 5.5V, IF = 10mA; single channel 5
Low Level Enable Voltage VEL 0.8 V VCC = 5.5V, IF = 10mA; single channel 5
Propagation Delay Time to Output High Level TPLH 20 75 ns RL = 350Ω, CL = 15pF, TA = 25°C (Fig. 20) 5
Propagation Delay Time to Output High Level TPLH 100 ns RL = 350Ω, CL = 15pF (Fig. 20) 5
Propagation Delay Time to Output Low Level TPHL 25 75 ns RL = 350Ω, CL = 15pF, TA = 25°C (Fig. 20) 5
Propagation Delay Time to Output Low Level TPHL 100 ns RL = 350Ω, CL = 15pF (Fig. 20) 5
Pulse Width Distortion /TPHL-TPLH/ 35 ns RL = 350Ω, CL = 15pF (Fig. 20) 5
Output Rise Time (10-90%) tr 50 ns RL = 350Ω, CL = 15pF (Fig. 20); single channel 5
Output Fall Time (90-10%) tf 12 ns RL = 350Ω, CL = 15pF (Fig. 20); single channel 5
Enable Propagation Delay Time to Output High Level tELH 20 ns IF = 7.5mA, VEH = 3.5V, RL = 350Ω, CL = 15pF (Fig. 21); HCPL0601 5
Enable Propagation Delay Time to Output Low Level tEHL 20 ns IF = 7.5mA, VEH = 3.5V, RL = 350Ω, CL = 15 pF (Fig. 21); HCPL0601 5
Common Mode Transient Immunity (at Output High Level) /CMH/ 10000 V/µs /VCM/ = 50V; RL = 350Ω, TA = 25°C, IF = 0mA, VOH (Min.) = 2.0 V (Fig. 22, 23); HCPL0601 5
Common Mode Transient Immunity (at Output Low Level) /CML/ 10000 V/µs /VCM/ = 50V; RL = 350Ω, TA = 25°C, IF = 7.5mA, VOL (Max.) = 0.8 V (Fig. 22, 23); HCPL0601 5
High Level Output Current IOH 100 µA VCC = 5.5V, VO = 5.5 V, IF = 250µA, VE = 2.0V 6
Low Level Output Voltage VOL 0.6 V VCC = 5.5V, IF = 5mA, VE = 2.0V, IOL = 13mA 6
Input Threshold Current IFT 5 mA VCC = 5.5V, VO = 0.6V, VE = 2.0V, IOL = 13mA 6
Withstand Insulation Test Voltage VISO 3750 VRMS RH < 50%, TA = 25°C, II-O ≤ 2µA, t = 1 min. 6
Resistance (Input to Output) RI-O 1012 Ω VI-O = 500V; printed as 1012 (exponent lost in extraction) 6

CAD (KiCad official)

  • Symbol: HCPL0601R2
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: hcpl0601r2-etched.step / hcpl0601r2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcpl0601r2.step / hcpl0601r2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (20 pp, sha256 67b0444313bbc15a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF