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HCPL-4200-000E

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Broadcom AVAGO Logic Output Optoisolators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

HCPL-4200-000E

Broadcom AVAGO · Logic Output Optoisolators · DIP-8

HCPL-4200-000E from Broadcom AVAGO, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I+ input Positive current loop input (LED anode side); mark state requires 12 mA min input current (recommended 14 to 24 mA) and space state at most 3 mA.
2 I- input Negative current loop input (LED cathode side), with input capacitance of 120 pF max measured between pins 1 and 2.
3 NC unconnected Not shown on the functional diagram, so no internal connection is indicated; pins 1, 2, 3 and 4 are treated as the input side.
4 NC unconnected Not shown on the functional diagram, so no internal connection is indicated; pins 1, 2, 3 and 4 are treated as the input side.
5 GND power_in Output-side ground, with a 0.1 uF bypass capacitor recommended between pins 8 and 5.
6 VE input Three-state output enable input; logic low 0 to 0.8 V enables the output and logic high 2.0 to 20 V puts the output in high impedance.
7 VO tri_state Open-collector-style three-state logic output compatible with TTL, LSTTL and CMOS, rated -0.5 V to 20 V and 25 mA average output current maximum.
8 VCC power_in Output-side supply voltage, recommended 4.5 V to 20 V, with absolute maximum of 20 V.

Key specifications

Parameter Value
Manufacturer Broadcom AVAGO
Package DIP-8
Category Optoisolators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VCC 4.5 20 Volts 5
Forward Input Current (SPACE) ISI 0 2 mA 5
Forward Input Current (MARK) IMI 14 24 mA 5
Operating Temperature TA 0 70 °C 5
Fan Out N 0 4 TTL Loads 5
Logic Low Enable Voltage VEL 0 0.8 Volts 5
Logic High Enable Voltage VEH 2 20 Volts 5
Supply Voltage VCC 0 20 Volts 5
Average Input Current II -30 30 mA 5
Peak Transient Input Current II 0.5 A <=1 μs pulse width, 300 pps 5
Enable Input Voltage VE -0.5 20 Volts 5
Output Voltage VO -0.5 20 Volts 5
Average Output Current IO 25 mA 5
Input Power Dissipation PI 90 mW Derate linearly above 70°C free air at 1.6 mW/°C (note 2) 8
Storage Temperature TSTG -55 125 °C 5
Operating Temperature TA -40 85 °C 5
Lead Solder Temperature 260 °C for 10 s (1.6 mm below seating plane) 5
External Air Gap (External Clearance) L(IO1) 7.1 mm Measured from input terminals to output terminals, shortest distance through air 5
External Tracking Path (External Creepage) L(IO2) 7.4 mm Measured from input terminals to output terminals, shortest distance path along body 5
Mark State Input Voltage VMI 2.52 2.75 Volts II = 20 mA; VE = Don't Care 6
Space State Input Voltage VSI 1.6 2.2 Volts II = 0.5 to 2.0 mA; VE = Don't Care 6
Mark State Input Current IMI 12 mA 6
Space State Input Current ISI 3 mA 6
Input Hysteresis Current IHYS 0.3 0.8 mA 6
Logic Low Output Voltage (4 TTL Loads) VOL 0.5 Volts IOL = 6.4 mA; II = 3 mA 6
Logic High Output Voltage VOH 2.4 Volts IOH = -2.6 mA; II = 12 mA 6
Output Leakage Current IOHH 100 μA VO = 5.5 V; II = 20 mA 6
Output Leakage Current IOHH 500 μA VO = 20 V 6
Logic High Enable Voltage VEH 2 Volts 6
Logic Low Enable Voltage VEL 0.8 Volts 6
Logic High Enable Current IEH 20 μA VE = 2.7 V 6
Logic High Enable Current IEH 100 μA VE = 5.5 V 6
Logic High Enable Current IEH 0.004 250 μA VE = 20 V 6
Logic Low Enable Current IEL -0.32 mA VE = 0.4 V 6
Logic Low Supply Current ICCL 4.5 6 mA VCC = 5.5 V; II = 0 mA 6
Logic Low Supply Current ICCL 5.25 7.5 mA VCC = 20 V 6
Logic High Supply Current ICCH 2.7 4.5 mA VCC = 5.5 V; II = 20 mA 6
Logic High Supply Current ICCH 3.1 6 mA VCC = 20 V 6
High Impedance Output Current IOZL -20 μA VO = 0.4 V; VE = 2 V 6
High Impedance Output Current IOZH 20 μA VO = 2.4 V 6
High Impedance Output Current IOZH 100 μA VO = 5.5 V 6
High Impedance Output Current IOZH 500 μA VO = 20 V 6
Logic Low Short Circuit Output Current IOSL 25 mA VO = VCC = 5.5 V; II = 0 mA 6
Logic Low Short Circuit Output Current IOSL 40 mA VO = VCC = 20 V; II = 0 mA 6
Logic High Short Circuit Output Current IOSH -10 mA VCC = 5.5 V; II = 20 mA 6
Logic High Short Circuit Output Current IOSH -25 mA VCC = 20 V 6
Propagation Delay Time to Logic High Output Level tPLH 0.23 1.6 μs VE = 0 V; CL = 15 pF 7
Propagation Delay Time to Logic Low Output Level tPHL 0.17 1 μs VE = 0 V; CL = 15 pF 7
Propagation Delay Time Skew tPLH - tPHL 60 ns II = 20 mA; CL = 15 pF 7
Output Enable Time to Logic Low Level tPZL 25 ns II = 0 mA; CL = 15 pF 7
Output Enable Time to Logic High Level tPZH 28 ns II = 20 mA; CL = 15 pF 7
Output Disable Time to Logic Low Level tPLZ 60 ns II = 0 mA; CL = 15 pF 7
Output Disable Time to Logic High Level tPHZ 105 ns II = 20 mA; CL = 15 pF 7
Common Mode Transient Immunity at Logic High Output Level /CMH/ 1000 10000 V/μs VCM = 50 V (peak); II = 12 mA; TA = 25°C 7
Common Mode Transient Immunity at Logic Low Output Level /CML/ 1000 10000 V/μs VCM = 50 V (peak); II = 3 mA; TA = 25°C 7
Input-Output Momentary Withstand Voltage VISO 3750 V rms RH ≤ 50%, t = 1 min, TA = 25°C 7
Resistance, Input-Output RI-O 1012 ohms VI-O = 500 V dc 7
Capacitance, Input-Output CI-O 1 pF f = 1 MHz; VI-O = 0 V 7

CAD (KiCad official)

  • Symbol: HCPL-4200-000E
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: hcpl-4200-000e-etched.step / hcpl-4200-000e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcpl-4200-000e.step / hcpl-4200-000e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom AVAGO datasheet (13 pp, sha256 750e59785c0c65c1, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF