component
HCPL-3140-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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HCPL-3140-500E
Broadcom AVAGO · Logic Output Optoisolators · DIP-8
HCPL-3140-500E from Broadcom AVAGO, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N/C | unconnected | No internal connection. |
| 2 | ANODE | passive | LED anode input; recommended LED on current IF(ON) is 8 to 12 mA. |
| 3 | CATHODE | passive | LED cathode input; LED off input voltage VF(OFF) is -3.6 V to 0.8 V. |
| 4 | N/C | unconnected | No internal connection. |
| 5 | VEE | power_in | Negative supply/ground reference for the output stage, with VCC-VEE of 10 V to 30 V recommended (absolute maximum 35 V). |
| 6 | VO | output | Gate drive output with 0.4 A minimum peak output current, high when the LED is on and low when it is off. |
| 7 | N.C. | unconnected | No internal connection. |
| 8 | VCC | power_in | Positive supply for the output stage, 10 V to 30 V relative to VEE, with a 0.1 µF bypass capacitor required between VCC and VEE. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | DIP-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High Level Output Current | IOH | 0.2 | A | Vo = VCC-4 | 6 | ||
| High Level Output Current | IOH | 0.4 | 0.5 | A | Vo = VCC-10 | 6 | |
| Low Level Output Current | IOL | 0.2 | 0.4 | A | Vo = VEE+2.5 | 6 | |
| Low Level Output Current | IOL | 0.4 | 0.5 | A | Vo = VEE+10 | 6 | |
| Low Level Output Voltage | VOL | 0.4 | 1 | V | Io = 100 mA | 6 | |
| High Level Supply Current | ICCH | 0.7 | 3 | mA | Io = 0 mA | 6 | |
| Low Level Supply Current | ICCL | 1.2 | 3 | mA | Io = 0 mA | 6 | |
| Input Forward Voltage | VF | 1.2 | 1.5 | 1.8 | V | IF = 10 mA | 6 |
| Propagation Delay Difference Between Any Two Parts or Channels | PDD | -0.5 | 0.5 | µs | IF = 8 mA, VCC = 30 V | 7 | |
| Propagation Delay Time to High Output Level | tPLH | 0.1 | 0.2 | 0.7 | µs | Rg = 47 Ω, Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% | 7 |
| Propagation Delay Time to Low Output Level | tPHL | 0.1 | 0.3 | 0.7 | µs | Rg = 47 Ω, Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% | 7 |
| Output High Level Common Mode Transient Immunity | /CMH/ | 25 | 35 | kV/µs | TA = 25°C, VCM = 1 kV | 7 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 25 | 35 | kV/µs | Vo < 1.0 V (note 12), Fig. 18 | 7 | |
| Power Supply | VCC-VEE | 10 | 30 | V | Recommended operating conditions | 6 | |
| Input Current (ON) | IF(ON) | 8 | 12 | mA | Recommended operating conditions | 6 | |
| Input Voltage (OFF) | VF(OFF) | -3.6 | 0.8 | V | Recommended operating conditions | 6 | |
| Operating Temperature | TA | -40 | 100 | °C | Recommended operating conditions | 6 | |
| Storage Temperature | TS | -55 | 125 | °C | Absolute maximum rating | 5 | |
| Operating Temperature | TA | -40 | 100 | °C | Absolute maximum rating | 5 | |
| Average Input Current | IF(AVG) | 25 | mA | Note 1: derate linearly above 70°C at 0.3 mA/°C | 5 | ||
| Peak Transient Input Current | IF(TRAN) | 1 | A | <1 µs pulse width, 300 pps | 5 | ||
| Reverse Input Voltage | VR | 5 | V | Absolute maximum rating | 5 | ||
| High Level Peak Output Current | IOH(PEAK) | 0.6 | A | Note 2: max pulse width 10 µs, max duty cycle 0.2% | 5 | ||
| Low Level Peak Output Current | IOL(PEAK) | 0.6 | A | Note 2: max pulse width 10 µs, max duty cycle 0.2% | 5 | ||
| Supply Voltage | VCC-VEE | -0.5 | 35 | V | Absolute maximum rating | 5 | |
| Output Voltage | VO(PEAK) | -0.5 | V | Maximum printed as VCC; not numeric in datasheet | 5 | ||
| Output Power Dissipation | PO | 250 | mW | Note 3: derate linearly above 85°C at 4.0 mW/°C | 5 | ||
| Input Power Dissipation | PI | 45 | mW | Note 4: no derating required | 5 | ||
| Lead Solder Temperature | 260 | °C | 10 sec, 1.6 mm below seating plane | 5 |
CAD (KiCad official)
- Symbol:
HCPL-3140-500E - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
hcpl-3140-500e-etched.step/hcpl-3140-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hcpl-3140-500e.step/hcpl-3140-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (16 pp, sha256
cb1d507936c96058, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).