component
HCPL-092J-500E
Public Made by Adomby adom
Broadcom AVAGO Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownHCPL-092J-500E
Broadcom AVAGO · Digital Isolators · SOIC-16
HCPL-092J-500E from Broadcom AVAGO, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power Supply 1 for the side-1 (input) circuitry, recommended 3.0 V to 5.5 V with a 47 nF low-ESR ceramic decoupling capacitor close to the pin. |
| 2 | GND1 | power_in | Power Supply Ground 1, the ground reference for VDD1 side. |
| 3 | IN1 | input | Logic Input Signal for channel 1, transmitted to OUT1 across the isolation barrier (max input -0.5 V to VDD1 + 0.5 V). |
| 4 | IN2 | input | Logic Input Signal for channel 2, transmitted to OUT2 across the isolation barrier (max input -0.5 V to VDD1 + 0.5 V). |
| 5 | IN3 | input | Logic Input Signal for channel 3, transmitted to OUT3 across the isolation barrier (max input -0.5 V to VDD1 + 0.5 V). |
| 6 | OUT4 | output | Logic Output Signal for channel 4, driven from IN4 on the opposite side (max output current drive 10 mA). |
| 7 | NC | unconnected | Not Connected. |
| 8 | GND1 | power_in | Power Supply Ground 1, the ground reference for VDD1 side. |
| 9 | GND2 | power_in | Power Supply Ground 2, the ground reference for VDD2 side. |
| 10 | NC | unconnected | Not Connected. |
| 11 | IN4 | input | Logic Input Signal for channel 4, transmitted to OUT4 across the isolation barrier (max input -0.5 V to VDD2 + 0.5 V). |
| 12 | OUT3 | output | Logic Output Signal for channel 3, driven from IN3 (max output current drive 10 mA). |
| 13 | OUT2 | output | Logic Output Signal for channel 2, driven from IN2 (max output current drive 10 mA). |
| 14 | OUT1 | output | Logic Output Signal for channel 1, driven from IN1 (max output current drive 10 mA). |
| 15 | GND2 | power_in | Power Supply Ground 2, the ground reference for VDD2 side. |
| 16 | VDD2 | power_in | Power Supply 2 for the side-2 (output) circuitry, recommended 3.0 V to 5.5 V with a 47 nF low-ESR ceramic decoupling capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | 150 | °C | 10 | ||
| Ambient Operating Temperature (absolute maximum) | TA | -55 | 125 | °C | 10 | ||
| Supply Voltage | VDD1, VDD2 | -0.5 | 7 | V | 10 | ||
| Input Voltage | VIN | -0.5 | V | 10 | |||
| Output Voltage | VOUT | -0.5 | V | 10 | |||
| Output Current Drive | IOUT | 10 | mA | 10 | |||
| Lead Solder Temperature (10s) | 260 | °C | 10s | 10 | |||
| ESD Human Body Model | 2 | kV | Human Body Model | 10 | |||
| Ambient Operating Temperature | TA | -40 | 100 | °C | 10 | ||
| Supply Voltage | VDD1, VDD2 | 3 | 5.5 | V | 10 | ||
| Logic High Input Voltage | VIH | 2.4 | V | 10 | |||
| Logic Low Input Voltage | VIL | 0 | 0.8 | V | 10 | ||
| Input Signal Rise and Fall Times | tIR, tIF | 1 | µs | 10 | |||
| Quiescent Supply Current 1 (3.3V operation) | IDD1 | 1.5 | 2 | mA | VIN = 0V | 11 | |
| Quiescent Supply Current 2 (3.3V operation) | IDD2 | 3 | 6 | mA | VIN = 0V | 11 | |
| Logic Input Current (3.3V operation) | IIN | -10 | 10 | µA | 11 | ||
| Logic Low Output Voltage (3.3V operation, low-current) | VOL | 0 | 0.1 | V | IOUT = 20 µA, VIN = VIL | 11 | |
| Logic Low Output Voltage (3.3V operation, 4 mA) | VOL | 0.5 | 0.8 | V | IOUT = 4 mA, VIN = VIL | 11 | |
| Maximum Data Rate (3.3V operation) | 100 | 110 | MBd | CL = 15 pF | 11 | ||
| Clock Frequency (3.3V operation) | fmax | 50 | MHz | 11 | |||
| Propagation Delay Time to Logic Low Output (3.3V operation) | tPHL | 12 | 18 | ns | 11 | ||
| Propagation Delay Time to Logic High Output (3.3V operation) | tPLH | 12 | 18 | ns | 11 | ||
| Pulse Width (3.3V operation) | tPW | 10 | ns | 11 | |||
| Pulse Width Distortion (3.3V operation) | /PWD/ | 2 | 3 | ns | 11 | ||
| Propagation Delay Skew (3.3V operation) | tPSK | 4 | 6 | ns | 11 | ||
| Output Rise Time 10% to 90% (3.3V operation) | tR | 2 | 4 | ns | 11 | ||
| Output Fall Time 10% to 90% (3.3V operation) | tF | 2 | 4 | ns | 11 | ||
| Channel-to-Channel Skew (Dual and Quad Channels, 3.3V operation) | tCSK | 2 | 3 | ns | 11 | ||
| Quiescent Supply Current 1 (5V operation) | IDD1 | 2.5 | 3 | mA | VIN = 0V | 12 | |
| Quiescent Supply Current 2 (5V operation) | IDD2 | 6 | 9 | mA | VIN = 0V | 12 | |
| Logic Input Current (5V operation) | IIN | -10 | 10 | µA | 12 | ||
| Logic Low Output Voltage (5V operation, low-current) | VOL | 0 | 0.1 | V | IOUT = 20 µA, VIN = VIL | 12 | |
| Logic Low Output Voltage (5V operation, 4 mA) | VOL | 0.5 | 0.8 | V | IOUT = 4 mA, VIN = VIL | 12 | |
| Common Mode Transient Immunity (Output Logic High or Logic Low, 5V operation) | /CMH/, /CML/ | 15 | 18 | kV/µs | Vcm = 1000V | 12 | |
| Package Power Dissipation (16-Pin SOIC Narrow Body) | PPD | 150 | mW | 9 | |||
| Thermal Resistance Junction-to-Case Top (16-Pin SOIC Narrow Body) | θJCT | 41 | °C/W | Thermocouple located at center underside of package | 9 |
CAD (KiCad official)
- Symbol:
HCPL-092J-500E - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
hcpl-092j-500e-etched.step/hcpl-092j-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hcpl-092j-500e.step/hcpl-092j-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (18 pp, sha256
f47d8c82c70d7616, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).