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HCPL-0721-500E

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Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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HCPL-0721-500E

Broadcom AVAGO · Logic Output Optoisolators · SO-8

HCPL-0721-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input-side (LED driver) supply; 4.5 V to 5.5 V recommended with absolute maximum 0 to 6.0 V, and a 0.01 µF to 0.1 µF bypass capacitor must be placed as close as possible between pins 1 and 4.
2 VI input CMOS logic input that drives the internal LED (LED on when low, off when high); VIH is 2.0 V to VDD1 and VIL is 0.0 V to 0.8 V, with absolute limits of −0.5 V to VDD1 + 0.5 V.
3 NC unconnected Anode of the internal LED; must be left unconnected for guaranteed data sheet performance.
4 GND1 power_in Input-side ground reference for VDD1 and VI; it is the bypass return for the 0.01 µF to 0.1 µF capacitor on pin 1.
5 GND2 power_in Output-side ground reference for VDD2 and VO; it is the bypass return for the 0.01 µF to 0.1 µF capacitor on pin 8.
6 VO output CMOS logic output of the detector IC with VOH at least 4.4 V at IO = −20 µA and VOL at most 0.1 V at IO = 20 µA; average output current is limited to 10 mA.
7 NC unconnected Not connected internally.
8 VDD2 power_in Output-side (detector) supply; 4.5 V to 5.5 V recommended with absolute maximum 0 to 6.0 V, and a 0.01 µF to 0.1 µF bypass capacitor must be placed as close as possible between pins 5 and 8.

Key specifications

Parameter Value
Manufacturer Broadcom AVAGO
Package SO-8
Category Optoisolators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TS -55 125 °C 6
Ambient Operating Temperature (absolute maximum) TA -40 85 °C 6
Supply Voltages VDD1, VDD2 0 6 V 6
Input Voltage VI -0.5 V 6
Output Voltage VO -0.5 V 6
Average Output Current IO 10 mA 6
Lead Solder Temperature 260 °C for 10 sec., 1.6 mm below seating plane 6
Ambient Operating Temperature TA -40 85 °C 7
Supply Voltages VDD1, VDD2 4.5 5.5 V 7
Logic High Input Voltage VIH 2 V 7
Logic Low Input Voltage VIL 0 0.8 V 7
Input Signal Rise and Fall Times tir, tif 1 ms 7
Logic High Output Voltage VOH 4.4 5 V IO = -20 μA, VI = VIH 7
Logic High Output Voltage VOH 4 4.8 V IO = -4 mA, VI = VIH 7
Logic Low Output Voltage VOL 0 0.1 V IO = 20 μA, VI = VIL 7
Logic Low Output Voltage VOL 0.1 V IO = 400 μA, VI = VIL 7
Logic Low Output Voltage VOL 0.5 1 V IO = 4 mA, VI = VIL 7
Logic Low Input Supply Current IDD1L 6 10 mA VI = 0V 7
Logic High Input Supply Current IDD1H 1.5 3 mA VI = VDD1 7
Output Supply Current (IDD2L) IDD2L 7.7 9 mA 7
Output Supply Current (IDD2H) IDD2H 5.8 9 mA 7
Input Current II -10 10 μA 7
Propagation Delay Time to Logic Low Output tPHL 20 40 ns CL= 15 pF 7
Propagation Delay Time to Logic High Output tPLH 19 40 ns 7
Pulse Width PW 40 ns 7
Data Rate 25 MBd 7
Pulse Width Distortion (HCPL-0721 / 7721 row) PWD 3 6 ns 7
Propagation Delay Skew tPSK 20 ns 7
Common Mode Transient Immunity at Logic High Output /CMH/ 10 20 kV/μs VI = VDD1, VO > 0.8 VDD1, VCM = 1000V 8
Common Mode Transient Immunity at Logic Low Output /CML/ 10 20 kV/μs VI = 0V, VO > 0.8V, VCM = 1000V 8
Input-Output Momentary Withstand Voltage (072X) VISO 3750 Vrms RH ≤ 50%, t = 1 min, TA = 25°C 8
Package Power Dissipation PPD 150 mW 8
Output Rise Time (10% to 90%) tR 9 ns 7
Output Fall Time (90% to 10%) tF 8 ns 7
Input Dynamic Power Dissipation Capacitance CPD1 60 pF 8
Output Dynamic Power Dissipation Capacitance CPD2 10 pF 8
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz 8
Input Capacitance CI 3 pF 8
Input IC Junction-to-Case Thermal Resistance (072X) θjci 160 °C/W 8
Output IC Junction-to-Case Thermal Resistance (072X) θjco 135 °C/W 8

CAD (KiCad official)

  • Symbol: HCPL-0721-500E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: hcpl-0721-500e-etched.step / hcpl-0721-500e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcpl-0721-500e.step / hcpl-0721-500e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom AVAGO datasheet (21 pp, sha256 c3761b4607c48cc8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF