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HCPL-0710-500E

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Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HCPL-0710-500E

Broadcom AVAGO · Logic Output Optoisolators · SO-8

HCPL-0710-500E from Broadcom AVAGO, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input-side supply pin; recommended supply is 4.5 V to 5.5 V, with a 0.01 µF to 0.1 µF bypass capacitor required between pins 1 and 4.
2 VI input CMOS logic input that drives the internal LED, with VIH 2.0 V to VDD1 and VIL 0.0 V to 0.8 V; the LED is on when VI is low.
3 NC unconnected Anode of the internal LED that must be left unconnected for guaranteed data sheet performance.
4 GND1 power_in Input-side ground reference for VDD1 and the LED driver, bypassed to pin 1.
5 GND2 power_in Output-side ground reference for VDD2 and the output driver, bypassed to pin 8.
6 VO output CMOS logic output from the detector comparator and output driver, which is high when the LED is off (VI high) and sources the logic-high level from VDD2.
7 NC unconnected Not connected internally and should be left unconnected.
8 VDD2 power_in Output-side supply pin; recommended supply is 4.5 V to 5.5 V, with a 0.01 µF to 0.1 µF bypass capacitor required between pins 5 and 8.

Key specifications

Parameter Value
Manufacturer Broadcom AVAGO
Package SO-8
Category Optoisolators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TS -55 125 °C 6
Ambient Operating Temperature TA -40 100 °C 6
Supply Voltages VDD1, VDD2 0 6 Volts 6
Input Voltage VI -0.5 Volts 6
Output Voltage VO -0.5 Volts 6
Input Current II -10 10 mA 6
Average Output Current IO 10 mA 6
Ambient Operating Temperature TA -40 100 °C 6
Supply Voltages VDD1, VDD2 4.5 5.5 V 6
Logic High Input Voltage VIH 2 V 6
Logic Low Input Voltage VIL 0 0.8 V 6
Input Signal Rise and Fall Times tr, tf 1 ms 6
Logic Low Input Supply Current IDD1L 6 10 mA VI = 0 V 7
Logic High Input Supply Current IDD1H 1.5 3 mA VI = VDDI 7
Input Supply Current IDD1 13 mA 7
Output Supply Current IDD2 5.5 11 mA 7
Input Current II -10 10 µA 7
Logic High Output Voltage VOH 4.4 5 V IO = -20 µA, VI = VIH 7
Logic High Output Voltage VOH 4 4.8 V IO = -4 mA, VI = VIH 7
Logic Low Output Voltage VOL 0 0.1 V IO = -20 µA, VI = VIL 7
Logic Low Output Voltage VOL 0.5 1 V IO = -4 mA, VI = VIL 7
Propagation Delay Time to Logic Low Output tPHL 20 40 ns CL = 15 pF, CMOS Signal Levels 7
Propagation Delay Time to Logic High Output tPLH 23 40 ns CL = 15 pF, CMOS Signal Levels 7
Pulse Width PW 80 ns CL = 15 pF, CMOS Signal Levels 7
Pulse Width Distortion PWD 3 8 ns /tPHL - tPLH/, CL = 15 pF, CMOS Signal Levels 7
Propagation Delay Skew tPSK 20 ns CL = 15 pF 7
Common Mode Transient Immunity at Logic High Output /CMH/ 10 20 kV/µs VI = VDD1, VO > 0.8 VDD1, VCM = 1000 V 7
Common Mode Transient Immunity at Logic Low Output /CML/ 10 20 kV/µs VI = 0 V, VO > 0.8 V, VCM = 1000 V 7
Input-Output Momentary Withstand Voltage (0710) VISO 3750 Vrms RH = 50%, t = 1 min., TA = 25 °C 8
Input IC Junction-to-Case Thermal Resistance (0710) θjci 160 °C/W Thermocouple located at center underside of package 8
Output IC Junction-to-Case Thermal Resistance (0710) θjco 135 °C/W 8
Package Power Dissipation PPD 150 mW 8
Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air 5
Minimum External Tracking (Creepage) L(I02) 4.8 mm Measured from input terminals to output terminals, shortest distance path along body 5
Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness between emitter and detector 5
Tracking Resistance (Comparative Tracking Index) CTI 175 V DIN IEC 112/VDE 0303 Part 1 5

CAD (KiCad official)

  • Symbol: HCPL-0710-500E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: hcpl-0710-500e-etched.step / hcpl-0710-500e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcpl-0710-500e.step / hcpl-0710-500e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom AVAGO datasheet (17 pp, sha256 f2ce4bb631586167, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF