component
HCPL-0370-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "Broadcom AVAGO Logic Output Optoisolators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"optoisolators",
"hcpl-0370-500e",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
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"files": [
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"README.md",
"hcpl-0370-500e.kicad_sym",
"hcpl-0370-500e.kicad_mod",
"hcpl-0370-500e.glb",
"hcpl-0370-500e.step",
"hcpl-0370-500e.lbr",
"docs/hero.png",
"docs/hcpl-0370-500e-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"hcpl-0370-500e-hero.glb",
"hcpl-0370-500e-hero.overlay.json",
"hcpl-0370-500e-etched.glb"
],
"component": {
"mpn": "HCPL-0370-500E",
"manufacturer": "Broadcom AVAGO",
"package": "SO-8",
"pin_count": 8,
"category": "Optoisolators",
"subcategory": "Logic Output Optoisolators",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589785498697687040",
"parts": {
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"model_3d_step": "hcpl-0370-500e-etched.step",
"model_3d_step_plain": "hcpl-0370-500e.step",
"lbr": "hcpl-0370-500e.lbr"
},
"distributor_links": {
"lcsc": "C692007"
},
"distributor_check": {
"checked_at": "2026-10-18T09:50:49Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "quota"
},
"mouser": {
"pn": null,
"status": "quota"
}
},
"pins": [
{
"number": "1",
"name": "AC",
"type": "input",
"description": "One of the two AC input terminals (with pin 4); the AC threshold is VTH+ 4.9 V typ and VTH- 3.7 V typ, measured as |V1 - V4|, with the input clamped by the internal diodes."
},
{
"number": "2",
"name": "DC+",
"type": "input",
"description": "Positive DC input terminal (with pin 3); the DC turn-on threshold is VTH+ 3.7 V typ and the turn-off threshold is VTH- 2.6 V typ, with the input current threshold ITH+ 2.5 mA typ for HCPL-0370."
},
{
"number": "3",
"name": "DC-",
"type": "input",
"description": "Negative DC input terminal (with pin 2); input voltage is measured as V2 - V3 and the DC input must not exceed the absolute maximum input voltage of -0.5 V on pins 2-3 as printed."
},
{
"number": "4",
"name": "AC",
"type": "input",
"description": "Second AC input terminal (with pin 1) for ac signals; the ac input thresholds are the same as for pin 1, VTH+ 4.9 V typ and VTH- 3.7 V typ."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the detector IC; VCC (pin 8) and output voltage (pin 6) are specified relative to this pin, with VCC absolute maximum of -0.5 V to 20 V."
},
{
"number": "6",
"name": "VO",
"type": "output",
"description": "Open-collector logic output referenced to pin 5; logic low VOL is 0.4 V max at VCC = 4.5 V and IOL = 4.2 mA, output voltage absolute maximum is -0.5 V to 20 V, and average output current is 30 mA max."
},
{
"number": "7",
"name": "NC",
"type": "unconnected",
"description": "No internal connection on the package."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage with recommended range 2 V to 18 V (absolute maximum 20 V); a 0.01 µF ceramic bypass capacitor between pins 8 and 5 is recommended to reduce supply noise."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet text contains no separate pin diagram for the SO-8 HCPL-0370 package. Pin numbers and ; NC on pin 7 comes from the DIP schematic only. The SO-8 HCPL-0370 pinout is not stated explicitly in; The text extraction order of the DIP schematic labels is scrambled. Pin assignments (AC on pins 1 an",
"1/8 pins cited to the wrong page (name found elsewhere): ['2:DC+@p8']"
],
"pages_sent": 14,
"cost_usd": 0.086,
"at": "2026-10-18T09:48:37"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589785498697687040",
"pages": 14,
"sha256": "0122d32590fa98ef",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
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"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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{
"file": "hcpl-0370-500e-etched.step",
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"extents_mm": [
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"sha256": "6b6b0ef9705b91f871a3b460745d75872b0b5d6e6cf8907c680d9746c603aab4",
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}