component
HCPL-0314-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHCPL-0314-500E
Broadcom AVAGO · Logic Output Optoisolators · SOP-8
HCPL-0314-500E from Broadcom AVAGO, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | N/C | unconnected | No internal connection. |
| 2 | ANODE | input | LED anode input; recommended LED on-current IF(ON) is 8 to 12 mA, with maximum average input current of 25 mA. |
| 3 | CATHODE | input | LED cathode input; the LED must be kept off with VF(OFF) between -3.6 V and 0.8 V, and reverse input voltage must not exceed 5 V. |
| 4 | N/C | unconnected | No internal connection. |
| 5 | VEE | power_in | Negative output supply (ground reference); VCC-VEE operates from 10 V to 30 V with a 0.1 µF bypass capacitor required between VCC and VEE. |
| 6 | VO | output | Gate-drive output, high when LED is on and low when LED is off, with 0.4 A minimum peak output current and a VOL maximum of 1 V at 100 mA. |
| 7 | N/C | unconnected | No internal connection. |
| 8 | VCC | power_in | Positive output supply; VCC-VEE operates from 10 V to 30 V (absolute maximum 35 V), requiring a 0.1 µF bypass capacitor to VEE. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SOP-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Operating Temperature | TA | -40 | 100 | °C | 5 | ||
| Average Input Current | IF(AVG) | 25 | mA | 5 | |||
| Peak Transient Input Current | IF(TRAN) | 1 | A | <1 µs pulse width, 300pps | 5 | ||
| Reverse Input Voltage | VR | 5 | V | 5 | |||
| High Level Peak Output Current | IOH(PEAK) | 0.6 | A | 5 | |||
| Low Level Peak Output Current | IOL(PEAK) | 0.6 | A | 5 | |||
| Supply Voltage | VCC-VEE | -0.5 | 35 | V | 5 | ||
| Output Voltage | VO(PEAK) | -0.5 | V | 5 | |||
| Output Power Dissipation | PO | 250 | mW | 5 | |||
| Input Power Dissipation | PI | 45 | mW | 5 | |||
| Lead Solder Temperature | 260 | °C | 10 sec., 1.6 mm below seating plane | 5 | |||
| Power Supply | VCC-VEE | 10 | 30 | V | 6 | ||
| Input Current (ON) | IF(ON) | 8 | 12 | mA | 6 | ||
| Input Voltage (OFF) | VF(OFF) | -3.6 | 0.8 | V | 6 | ||
| Operating Temperature | TA | -40 | 100 | °C | 6 | ||
| High Level Output Current | IOH | 0.2 | A | Vo = VCC-4 | 6 | ||
| High Level Output Current | IOH | 0.4 | 0.5 | A | Vo = VCC-10 | 6 | |
| Low Level Output Current | IOL | 0.2 | 0.4 | A | Vo = VEE+2.5 | 6 | |
| Low Level Output Current | IOL | 0.4 | 0.5 | A | Vo = VEE+10 | 6 | |
| Low Level Output Voltage | VOL | 0.4 | 1 | V | Io = 100 mA | 6 | |
| High Level Supply Current | ICCH | 0.7 | 3 | mA | Io = 0 mA | 6 | |
| Low Level Supply Current | ICCL | 1.2 | 3 | mA | Io = 0 mA | 6 | |
| Threshold Input Current Low to High | IFLH | 7 | mA | Io = 0 mA, Vo>5 V | 6 | ||
| Threshold Input Voltage High to Low | VFHL | 0.8 | V | High to Low | 6 | ||
| Input Forward Voltage | VF | 1.2 | 1.5 | 1.8 | V | IF = 10 mA | 6 |
| Input Reverse Breakdown Voltage | BVR | 5 | V | IR = 10 µA | 6 | ||
| Propagation Delay Time to High Output Level | tPLH | 0.1 | 0.2 | 0.7 | µs | Rg = 47 Ω, Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% | 7 |
| Propagation Delay Time to Low Output Level | tPHL | 0.1 | 0.3 | 0.7 | µs | Rg = 47 Ω, Cg = 3 nF, f = 10 kHz, Duty Cycle = 50% | 7 |
| Propagation Delay Difference Between Any Two Parts or Channels | PDD | -0.5 | 0.5 | µs | IF = 8 mA, VCC = 30 V | 7 | |
| Output High Level Common Mode Transient Immunity | /CMH/ | 25 | 35 | kV/µs | TA = 25°C, VCM = 1 kV | 7 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 25 | 35 | kV/µs | 7 | ||
| Input-Output Momentary Withstand Voltage | VISO | 3750 | Vrms | TA=25°C, RH<50% for | 7 | ||
| Input-Output Resistance | RI-O | 1012 | Ω | VI-O=500 V | 7 | ||
| Minimum External Air Gap (Clearance) | L(101) | 4.9 | mm | Measured from input terminals to output terminals, shortest distance through air | 5 | ||
| Minimum External Tracking (Creepage) | L(102) | 4.8 | mm | Measured from input terminals to output terminals, shortest distance path along body | 5 | ||
| Minimum Internal Plastic Gap (Internal Clearance) | 0.08 | mm | Through insulation distance, conductor to conductor | 5 | |||
| Tracking Resistance (Comparative Tracking Index) | CTI | 175 | V | DIN IEC 112/VDE 0303 Part 1 | 5 | ||
| Temperature Coefficient of Input Forward Voltage | DVF/DTA | -1.6 | mV/°C | 6 | |||
| Input Capacitance | CIN | 60 | pF | f = 1 MHz, VF = 0 V | 6 | ||
| Rise Time | tR | 50 | ns | 7 | |||
| Fall Time | tF | 50 | ns | 7 | |||
| Input-Output Capacitance | CI-O | 0.6 | pF | Freq=1 MHz | 7 |
CAD (KiCad official)
- Symbol:
HCPL-0314-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hcpl-0314-500e-etched.step/hcpl-0314-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hcpl-0314-500e.step/hcpl-0314-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (16 pp, sha256
cb1d507936c96058, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).