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HCM3043-QFN48

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XHSC Microcontrollers (MCU/MPU/SOC), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HCM3043-QFN48

XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(7x7)

HCM3043-QFN48 from XHSC, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTHI input External high-speed crystal/resonator input for the 4-32 MHz XTH oscillator, with injection current limited to ±5 mA.
2 XTHO output External high-speed crystal/resonator output for the 4-32 MHz XTH oscillator.
3 RESETB input Active-low reset input (CMOS) with a non-disconnectable weak pull-up of about 80 kΩ, VIL max 0.8 V and VIH min 0.8×VCC, injection current ±5 mA.
4 PC00 bidirectional General-purpose I/O (PC00) multiplexed with UART1_CTS, ADC input AIN10 and comparator inputs VC0_INP0 / VC1_INN0.
5 PC01 bidirectional General-purpose I/O (PC01) multiplexed with TIM5_CHB, UART1_RTS, ADC input AIN11 and comparator inputs VC0_INP1 / VC1_INN1.
6 PC02 bidirectional General-purpose I/O (PC02) multiplexed with SPI1_MISO, ADC input AIN12 and comparator inputs VC0_INP2 / VC1_INN2.
7 PC03 bidirectional General-purpose I/O (PC03) multiplexed with SPI1_MOSI, ADC input AIN13 and comparator inputs VC0_INP3 / VC1_INN3.
8 AVCC_MCU power_in Analog supply for the MCU (ADC, comparators, OPA); decoupling capacitor should be placed close to the pin.
9 PA00 bidirectional General-purpose I/O (PA00) multiplexed with UART1_CTS, timer functions, VC0_OUT, ADC input AIN0 and comparator inputs.
10 PA01 bidirectional General-purpose I/O (PA01) multiplexed with UART1_RTS, timer functions, HCLK_OUT, SPI1_MOSI, ADC input AIN1 and comparator inputs.
11 PA03 bidirectional General-purpose I/O (PA03) multiplexed with UART1_RXD, timer functions, SPI1_CS, ADC input AIN3 and comparator input VC0_INP7.
12 PA04 bidirectional General-purpose I/O (PA04) multiplexed with SPI0_CS, UART1_TXD, PCA_CH4, LVD_OUT, ADC input AIN4 and comparator input VC0_INP8.
13 PA05 bidirectional General-purpose I/O (PA05) multiplexed with SPI0_SCK, TIM0_ETR, PCA_ECI, XTL_OUT/XTH_OUT, ADC input AIN5 and comparator input VC0_INP9.
14 PA06 bidirectional General-purpose I/O (PA06) multiplexed with SPI0_MISO, PCA_CH0, TIM3_BK, VC0_OUT, ADC input AIN6 and comparator input VC0_INP10.
15 PA07 bidirectional General-purpose I/O (PA07) multiplexed with SPI0_MOSI, PCA_CH1, HCLK_OUT, VC1_OUT, ADC input AIN7 and comparator input VC0_INP11.
16 PB00 bidirectional General-purpose I/O (PB00) multiplexed with PCA_CH2, TIM3_CH1B, TIM5_CHB, RCH/RCL/PLL outputs, ADC input AIN8 and comparator inputs.
17 PB01 bidirectional General-purpose I/O (PB01) multiplexed with PCA_CH3, PCLK_OUT, TIM3_CH2B and TIM6_CHB; analog alternate functions are not in the provided text.
18 PB02 bidirectional General-purpose I/O (PB02) multiplexed with PCA_ECI, TIM4_CHA, TIM1_BK, TIM0_BK and TIM2_BK; analog alternate functions are not in the provided text.
19 PB10 bidirectional General-purpose I/O (PB10) multiplexed with I2C1_SCL, SPI1_SCK, TIM1_CHA, TIM3_CH1A and UART1_RTS.
20 PB11 bidirectional General-purpose I/O (PB11) multiplexed with I2C1_SDA, TIM1_CHB, TIM2_GATE, TIM6_CHA and UART1_CTS.
21 VSS_DRIVER power_in Ground reference for the gate driver; all gate-driver absolute maximum ratings are referenced to this pin.
22 LO3 output Low-side gate driver output for phase 3 (1 A source/sink drive capability).
23 LO2 output Low-side gate driver output for phase 2 (1 A source/sink drive capability).
24 LO1 output Low-side gate driver output for phase 1 (1 A source/sink drive capability).
25 VCC_DRIVER power_in Low-side and logic supply for the gate driver, absolute maximum -0.3 V to 20 V and operating range 5.5 V to 20 V.
26 VS3 passive High-side floating supply offset (phase 3 output reference), rated VB3−20 V to VB3+0.3 V.
27 HO3 output High-side gate driver output for phase 3, referenced to VS3.
28 VB3 power_in High-side floating supply for phase 3 driver; absolute maximum 45 V referenced to VSS_DRIVER.
29 VS2 passive High-side floating supply offset (phase 2 output reference), rated VB2−20 V to VB2+0.3 V.
30 HO2 output High-side gate driver output for phase 2, referenced to VS2.
31 VB2 power_in High-side floating supply for phase 2 driver; absolute maximum 45 V referenced to VSS_DRIVER.
32 VS1 passive High-side floating supply offset (phase 1 output reference), rated VB1−20 V to VB1+0.3 V.
33 HO1 output High-side gate driver output for phase 1, referenced to VS1.
34 VB1 power_in High-side floating supply for phase 1 driver; absolute maximum 45 V referenced to VSS_DRIVER.
35 VSS_LDO power_in Ground reference for the internal LDO regulator and the MCU supply limits.
36 VIN_LDO power_in LDO input: 5.5 V to 15 V with Hall sensor (60 mA) or 5.5 V to 25 V sensorless (30 mA).
37 VOUT_LDO power_out Regulated 5.0 V (±2%) LDO output, rated up to 30 mA sensorless or 60 mA with Hall sensor.
38 TEST passive Test pin; the provided datasheet text gives no function, limit or connection requirement for it.
39 PA13 bidirectional General-purpose I/O (PA13) multiplexed with IR_OUT, UART0_RXD, LVD_OUT and TIM3_ETR.
40 PD07 bidirectional General-purpose I/O (PD07) multiplexed with I2C1_SDA and UART0_RTS.
41 PA14 bidirectional General-purpose I/O (PA14) multiplexed with UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, and RCH/RCL/PLL outputs.
42 PB03 bidirectional General-purpose I/O (PB03) multiplexed with SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A and XTL/XTH outputs.
43 PB04 bidirectional General-purpose I/O (PB04) multiplexed with SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B, and comparator inputs VC0_INP12 / VC1_INP12 / VC1_INN10.
44 PB07 bidirectional General-purpose I/O (PB07) multiplexed with I2C0_SDA, UART0_RXD, TIM2_CHB, TIM0_CHB, LVD_IN2 and comparator inputs VC0_INP15 / VC1_INP15.
45 PD03 input MODE pin: high level enters ISP online programming mode, low level selects user mode.
46 PB08 bidirectional General-purpose I/O (PB08) multiplexed with I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, TIM3_CH2A, UART0_TXD and LVD_IN1 low-voltage detect input.
47 VCC_MCU power_in Main MCU digital supply, absolute maximum 5.5 V and operating range 1.8 V to 5.5 V.
48 VCAP power_out LDO core-supply output for internal circuits only; requires an external decoupling capacitor of at least 1 µF.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer XHSC
Package QFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-side floating supply absolute voltage (VB) VB -0.3 45 V 38
Logic input signal voltage VHIN1,2,3, VLIN1,2,3, ENB -0.3 20 V 38
Low-side supply and logic supply voltage (VCC_DRIVER) VCC_Driver -0.3 20 V 38
Low-side output voltage (lower limit; upper limit printed as VCC+0.3) VLO -0.3 V 38
Power dissipation (design value) PD 1.2 W TA≤25°C 38
Junction-to-ambient thermal resistance (design value) RthJA 30 °C /W 38
Allowable voltage slew rate dV/dt 50 V/ns 38
Junction temperature range (gate driver table) TJ -40 150 ℃ 38
Storage temperature (gate driver table) TS -40 150 ℃ 38
External main supply voltage (DVCC) VCC_MCU - VSS_LDO -0.3 5.5 V 39
Voltage difference between supply pins /ΔVCCx/ 50 mV 39
Voltage difference between ground pins /VSSx - VSS/ 50 mV 39
Total current through DVCC supply line IVCC_MCU 300 mA 39
Total current through VSS ground line IVSS_MCU 300 mA 39
Output sink current, any I/O and control pin IIO 25 mA 39
Output current, any I/O and control pin (printed -25 mA) IIO -25 mA 39
Injection current on RESETB pin IINJ(PIN) -5 5 mA 39
Injection current on XTHI and XTLI pins IINJ(PIN) -5 5 mA 39
Injection current on other pins IINJ(PIN) -5 5 mA 39
Total injection current on all I/O and control pins ∑IINJ(PIN) -25 25 mA 39
Storage temperature range (MCU) TSTG -60 150 ℃ 40
Maximum junction temperature (MCU) TJ 105 ℃ 40
LDO input voltage (Hall) Vin_LDO 5.5 15 V Iout=60mA（HALL） 38
LDO input voltage (sensorless) Vin_LDO 25 V Iout=30mA（SENSEOR LESS） 38
Maximum output current (sensorless, footnote 1 gives 30/60 mA) Iout(Max.) 30 mA Vin-Vout=1V 38
Maximum output current (Hall, footnote 1 gives 30/60 mA) Iout(Max.) 60 mA Vin-Vout=1V 38
Line regulation △Vout/△Vin×Vout 0.2 0.3 %/V Iout=10mA, 4V≤Vin≤40V 38
Load regulation 20 40 mV Vin=SetVout+1V, 1mA≤Iout≤50mA 38
Quiescent current Iq 2.5 5 uA Vin=Set Vout+1V 38
Output voltage temperature coefficient △Vout/△T×Vout -100 100 ppm/℃ Iout=10mA 39
Rise time (turn-on, gate driver) tr 37 30 ns VHIN1,2,3 or VLIN1,2,3=5V, VS1,2,3=0 45
Turn-on propagation delay ton 120 200 ns VHIN1,2,3 or VLIN1,2,3=5V, VS1,2,3=0 45
Turn-off propagation delay toff 120 200 ns VHIN1,2,3 or VLIN1,2,3=0, VS1,2,3=0 45
Fall time (turn-off, gate driver) tf 30 30 ns VHIN1,2,3 or VLIN1,2,3=0, VS1,2,3=0 45
Dead time (low-side off to high-side on, or high-side off to low-side on) DT 300 500 700 ns VHIN1,2,3 or VLIN1,2,3=0 and 5V, without external dead time 45
VCC_DRIVER quiescent current IQCC1 210 330 450 uA VHIN1,2,3 or VLIN1,2,3=5V, VENB=0 46
Standby-mode VCC_DRIVER quiescent current IQCC2 46 80 uA VHIN1,2,3 or VLIN1,2,3=5V, VENB=5 46
VCC_DRIVER undervoltage release voltage (rising) VCCUV+ 2.9 4.2 5.5 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
VCC_DRIVER undervoltage threshold voltage (falling) VCCUV- 2.5 3.8 5.1 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
VBS undervoltage release voltage (rising) VBSUV+ 2.5 3.8 5.5 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
VBS undervoltage threshold voltage (falling) VBSUV- 2.2 3.5 4.8 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
VBS quiescent current IQBS 25 45 65 uA VBS=15V 46
High-side leakage current ILK 10 uA VB=VS=100V VCC=0V 46
Logic-1 input level VIH 2.5 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
Logic-0 input level VIL 0.8 V VBIAS(VCC,VBS)=12V, Ta=25℃ 46
Internal 2.5V reference voltage (25°C) VREF25 2.475 2.5 2.525 V 常温25°C 3.3V 45
Internal 2.5V reference voltage (-40 to 85°C, evaluation data) VREF25 2.463 2.5 2.525 V -40C85C; 2.8V5.5V 45
Internal 1.5V reference voltage (25°C) VREF15 1.485 1.5 1.515 V 常温25°C 3.3V 45
Internal 1.5V reference voltage (-40 to 85°C, evaluation data) VREF15 1.477 1.5 1.519 V -40C85C; 1.8V5.5V 45
External input voltage range (upper limit printed as VCC) Vex 0 V 44
LVD detection threshold Vlevel 1.7 1.8 1.9 V LVD_CR.VTDS=0000 44
LVD detection threshold Vlevel 1.8 1.9 2 V LVD_CR.VTDS=0001 44
LVD detection threshold Vlevel 1.9 2 2.1 V LVD_CR.VTDS=0010 44
LVD detection threshold Vlevel 2 2.1 2.2 V LVD_CR.VTDS=0011 44
LVD detection threshold Vlevel 2.1 2.2 2.3 V LVD_CR.VTDS=0100 44
LVD detection threshold Vlevel 2.2 2.3 2.4 V LVD_CR.VTDS=0101 44
LVD detection threshold Vlevel 2.3 2.4 2.5 V LVD_CR.VTDS=0110 44
LVD detection threshold Vlevel 2.4 2.5 2.6 V LVD_CR.VTDS=0111 44
LVD detection threshold Vlevel 2.5 2.6 2.7 V LVD_CR.VTDS=1000 44
LVD detection threshold Vlevel 2.6 2.7 2.8 V LVD_CR.VTDS=1001 44

CAD (KiCad official)

  • Symbol: HCM3043-QFN48
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: hcm3043-qfn48-etched.step / hcm3043-qfn48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcm3043-qfn48.step / hcm3043-qfn48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (69 pp, sha256 421e9a181a504351, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF