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HCF4021YM013TR
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STMicroelectronics Shift Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# HCF4021YM013TR++**STMicroelectronics** · Shift Registers · SO-16++HCF4021YM013TR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PI-8 | input | Parallel input to stage 8 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 2 | Q6 | output | Buffered Q output from shift register stage 6. |+| 3 | Q7 | output | Buffered Q output from shift register stage 7. |+| 4 | PI-4 | input | Parallel input to stage 4 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 5 | PI-3 | input | Parallel input to stage 3 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 6 | PI-2 | input | Parallel input to stage 2 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 7 | PI-1 | input | Parallel input to stage 1 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 8 | VSS | power_in | Negative supply voltage (ground reference). |+| 9 | PARALLEL/SERIAL CONTROL | input | Parallel/serial control input; low selects serial shift mode, high selects parallel jam mode. |+| 10 | CLOCK | input | Clock input; positive edge triggers synchronous data entry in the selected mode. |+| 11 | SERIAL IN | input | Serial data input for shifting data into the register when parallel/serial control input is low. |+| 12 | Q8 | output | Buffered Q output from shift register stage 8 (final serial output). |+| 13 | PI-5 | input | Parallel input to stage 5 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 14 | PI-6 | input | Parallel input to stage 6 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 15 | PI-7 | input | Parallel input to stage 7 of the shift register for asynchronous jam entry when parallel/serial control input is high. |+| 16 | VDD | power_in | Positive supply voltage; operating range 3 to 20 V per recommended operating conditions. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `HCF4021YM013TR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SO-16 (KiCad packages3D, STEP)+- 3D model files: `hcf4021ym013tr-etched.step` / `hcf4021ym013tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hcf4021ym013tr.step` / `hcf4021ym013tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224443873398784) (13 pp, sha256 `b0614a47daab20a5`, retrieved 2026-10-06, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hcf4021ym013tr-datasheet.pdf)
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low selects serial shift mode, high selects parallel jam mode."+ },+ {+ "number": "10",+ "name": "CLOCK",+ "type": "input",+ "description": "Clock input; positive edge triggers synchronous data entry in the selected mode."+ },+ {+ "number": "11",+ "name": "SERIAL IN",+ "type": "input",+ "description": "Serial data input for shifting data into the register when parallel/serial control input is low."+ },+ {+ "number": "12",+ "name": "Q8",+ "type": "output",+ "description": "Buffered Q output from shift register stage 8 (final serial output)."+ },+ {+ "number": "13",+ "name": "PI-5",+ "type": "input",+ "description": "Parallel input to stage 5 of the shift register for asynchronous jam entry when parallel/serial control input is high."+ },+ {+ "number": "14",+ "name": "PI-6",+ "type": "input",+ "description": "Parallel input to stage 6 of the shift register for asynchronous jam entry when parallel/serial control input is high."+ },+ {+ "number": "15",+ "name": "PI-7",+ "type": "input",+ "description": "Parallel input to stage 7 of the shift register for asynchronous jam entry when parallel/serial control input is high."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage; operating range 3 to 20 V per recommended operating conditions."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 13,+ "cost_usd": 0.1071,+ "at": "2026-10-06T16:35:34"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224443873398784",+ "pages": 13,+ "sha256": "b0614a47daab20a5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}