component

HCF40106YM013TR

Public Made by Adom

by adom

STMicroelectronics Inverters, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs hcf40106ym013tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
hcf40106ym013tr-etched.fit.json hcf40106ym013tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
hcf40106ym013tr-etched.glb hcf40106ym013tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
hcf40106ym013tr-etched.step hcf40106ym013tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
hcf40106ym013tr.glb Publish 0.1.0 · Ray
hcf40106ym013tr.kicad_mod Publish 0.1.0 · Ray
hcf40106ym013tr.kicad_sym Publish 0.1.0 · Ray
hcf40106ym013tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
hcf40106ym013tr.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json hcf40106ym013tr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md hcf40106ym013tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

HCF40106YM013TR

STMicroelectronics · Inverters · SOP-14

HCF40106YM013TR from STMicroelectronics, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Schmitt trigger input A for inverter 1. Input voltage range 0 to VDD (recommended). Positive trigger threshold VP typ. 2.9 V @ VDD=5 V; negative trigger threshold VN typ. 1.9 V @ VDD=5 V. Protected by COS/MOS protection network.
2 G output Inverter 1 output (G = /A). Standard symmetrical CMOS output; IOH typ. -3.2 mA @ VDD=5 V, IOL typ. 1 mA @ VDD=5 V. VOH ≥ 4.95 V and VOL ≤ 0.05 V at VDD = 5 V with
3 B input Schmitt trigger input B for inverter 2. Same electrical characteristics as input A. Protected by COS/MOS protection network (diodes to VDD and VSS with series resistor).
4 H output Inverter 2 output (H = /B). Standard symmetrical CMOS output; drive characteristics identical to output G.
5 C input Schmitt trigger input C for inverter 3. Same electrical characteristics as input A. Protected by COS/MOS protection network.
6 I output Inverter 3 output (I = /C). Standard symmetrical CMOS output; drive characteristics identical to output G.
7 VSS power_in Negative supply / ground reference. All voltages in the datasheet are referenced to VSS. Typically tied to 0 V.
8 J output Inverter 4 output (J = /D). Standard symmetrical CMOS output; drive characteristics identical to output G.
9 D input Schmitt trigger input D for inverter 4. Same electrical characteristics as input A. Protected by COS/MOS protection network.
10 K output Inverter 5 output (K = /E). Standard symmetrical CMOS output; drive characteristics identical to output G.
11 E input Schmitt trigger input E for inverter 5. Same electrical characteristics as input A. Protected by COS/MOS protection network.
12 L output Inverter 6 output (L = /F). Standard symmetrical CMOS output; drive characteristics identical to output G.
13 F input Schmitt trigger input F for inverter 6. Same electrical characteristics as input A. Protected by COS/MOS protection network.
14 VDD power_in Positive supply voltage. Recommended range 3 V to 20 V; absolute maximum -0.5 V to +22 V. Should be bypassed to VSS with a decoupling capacitor near the pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • HCF40106YM013TR

CAD (KiCad official)

  • Symbol: HCF40106YM013TR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: hcf40106ym013tr-etched.step / hcf40106ym013tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hcf40106ym013tr.step / hcf40106ym013tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
hcf40106ym013tr.step 195 KB You want the bare part, or you mark your own boards.
hcf40106ym013tr-etched.step 3.1 MB You want the part with HCF40106YM013TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 779 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (16 pp, sha256 3a678ff5cb0fd5b4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF