component
HC32L190JCTA-LQ48
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHC32L190JCTA-LQ48
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
HC32L190JCTA-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCAP | power_out | LDO core-supply output for internal circuits only, requiring an external decoupling capacitor of not less than 1 uF. |
| 2 | PC13 | bidirectional | GPIO with alternate functions RTC_1HZ, TIM3_CH1B and LVD0 (low-voltage detect monitor input). |
| 3 | XTLI/PC14 | input | Low-speed external crystal (32.768 kHz) oscillator input, also usable as GPIO PC14; crystal load capacitance must follow the crystal maker's specification. |
| 4 | XTLO/PC15 | output | Low-speed external crystal (32.768 kHz) oscillator output, also usable as GPIO PC15; crystal load capacitance must follow the crystal maker's specification. |
| 5 | XTHI/PF00 | bidirectional | High-speed external crystal/resonator (4 to 32 MHz) oscillator input, also GPIO PF00 with alternate functions I2C0_SDA and UART1_TXD. |
| 6 | XTHO/PF01 | output | High-speed external crystal/resonator (4 to 32 MHz) oscillator output, also GPIO PF01 with alternate functions I2C0_SCL, TIM4_CHB and UART1_RXD. |
| 7 | RESETB | input | Active-low reset input with a non-disconnectable weak pull-up (about 80 kΩ); pulses shorter than 100 ns are filtered and pulses longer than 300 ns are not filtered. |
| 8 | AVSS | power_in | Analog ground, which must be connected to the external supply system within the allowed range. |
| 9 | AVCC | power_in | Analog supply, which must be the same voltage as DVCC (1.8 to 5.5 V operating range). |
| 10 | PA00 | bidirectional | GPIO with alternate functions UART1_CTS, LPUART1_TXD, TIM0_ETR, VC0_OUT, TIM1_CHA, TIM3_ETR, TIM0_CHA and ADC input AIN0. |
| 11 | PA01 | bidirectional | GPIO with alternate functions UART1_RTS, LPUART1_RXD, TIM0_CHB, TIM1_ETR, TIM1_CHB, HCLK_OUT and SPI1_MOSI, and ADC input AIN1. |
| 12 | PA02 | bidirectional | GPIO with alternate functions UART1_TXD, TIM0_CHA, VC1_OUT, TIM1_CHA, TIM2_CHA, PCLK_OUT and SPI1_MISO, and ADC input AIN2. |
| 13 | PA03 | bidirectional | GPIO with alternate functions UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A and TIM5_CHA, and ADC input AIN3. |
| 14 | PA04 | bidirectional | GPIO with alternate functions SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT and TIM3_CH2B, plus ADC input AIN4, DAC_OUT and OPA_OUT0. |
| 15 | PA05 | bidirectional | GPIO with alternate functions SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT and XTH_OUT. |
| 16 | PA06 | bidirectional | GPIO with alternate functions SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT, TIM3_GATE and LPUART0_CTS. |
| 17 | PA07 | bidirectional | GPIO with alternate functions SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT and TIM4_CHB. |
| 18 | PB00 | bidirectional | GPIO with alternate functions PCA_CH2, TIM3_CH1B, LPUART0_TXD, TIM5_CHB, RCH_OUT, RCL_OUT and PLL_OUT. |
| 19 | PB01 | bidirectional | GPIO with alternate functions PCA_CH3, PCLK_OUT, TIM3_CH2B, TIM6_CHB, LPUART0_RTS, VC2_OUT and TCLK_OUT. |
| 20 | PB02 | bidirectional | GPIO with alternate functions LPTIM_TOG, PCA_ECI, LPUART1_TXD, TIM4_CHA, TIM1_BK, TIM0_BK and TIM2_BK. |
| 21 | PB10 | bidirectional | GPIO with alternate functions I2C1_SCL, SPI1_SCK, TIM1_CHA, LPUART0_TXD, TIM3_CH1A, LPUART1_RTS and UART1_RTS. |
| 22 | PB11 | bidirectional | GPIO with alternate functions I2C1_SDA, TIM1_CHB, LPUART0_RXD, TIM2_GATE, TIM6_CHA, LPUART1_CTS and UART1_CTS. |
| 23 | DVSS | power_in | Digital ground, which must be connected to the external supply system within the allowed range. |
| 24 | DVCC | power_in | Digital supply, which must be the same voltage as AVCC (1.8 to 5.5 V operating range) and needs its own decoupling capacitor placed close to the pin. |
| 25 | PB12 | bidirectional | GPIO with alternate functions SPI1_CS, TIM3_BK, LPUART0_TXD, TIM0_BK, LPUART0_RTS and TIM6_CHA. |
| 26 | PB13 | bidirectional | GPIO with alternate functions SPI1_SCK, I2C1_SCL, TIM3_CH0B, LPUART0_CTS, TIM1_CHA, TIM1_GATE and TIM6_CHB. |
| 27 | PB14 | bidirectional | GPIO with alternate functions SPI1_MISO, I2C1_SDA, TIM3_CH1B, TIM0_CHA, RTC_1HZ, LPUART0_RTS and TIM1_BK. |
| 28 | PB15 | bidirectional | GPIO with alternate functions SPI1_MOSI, TIM3_CH2B, TIM0_CHB, TIM0_GATE and LPUART1_RXD. |
| 29 | PA08 | bidirectional | GPIO with alternate functions UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA and TIM3_BK. |
| 30 | PA09 | bidirectional | GPIO with alternate functions UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT and TIM5_CHA. |
| 31 | PA10 | bidirectional | GPIO with alternate functions UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT and TIM6_CHA. |
| 32 | PA11 | bidirectional | GPIO with alternate functions UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO and TIM4_CHB. |
| 33 | PA12 | bidirectional | GPIO with alternate functions UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT, SPI0_MOSI and PCNT_S0. |
| 34 | PA13/SWDIO | bidirectional | SWD debug data I/O, also GPIO with alternate functions IR_OUT, UART0_RXD, LVD_OUT, TIM3_ETR, RTC_1HZ, PCNT_S1 and VC2_OUT. |
| 35 | PF06 | bidirectional | GPIO with alternate functions I2C1_SCL, LPUART1_CTS and UART0_CTS. |
| 36 | PF07 | bidirectional | GPIO with alternate functions I2C1_SDA, LPUART1_RTS and UART0_RTS. |
| 37 | PA14/SWCLK | input | SWD debug clock input, also GPIO with alternate functions UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT and PLL_OUT. |
| 38 | PA15 | bidirectional | GPIO with alternate functions SPI0_CS, UART1_RXD, LPUART1_RTS, TIM0_ETR, TIM0_CHA and TIM3_CH1A. |
| 39 | PB03 | bidirectional | GPIO with alternate functions SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, LPTIM_GATE, XTL_OUT and XTH_OUT. |
| 40 | PB04 | bidirectional | GPIO with alternate functions SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B and LPTIM_ETR. |
| 41 | PB05 | bidirectional | GPIO with alternate functions SPI0_MOSI, TIM1_BK, PCA_CH1, LPTIM_GATE, PCNT_S0 and UART0_RTS. |
| 42 | PB06 | bidirectional | GPIO with alternate functions I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA, LPTIM_ETR, TIM3_CH0A and LPTIM_TOG. |
| 43 | PB07 | bidirectional | GPIO with alternate functions I2C0_SDA, UART0_RXD, TIM2_CHB, LPUART1_CTS, TIM0_CHB, LPTIM_TOGN and PCNT_S1, and also an LVD monitor input. |
| 44 | BOOT0 | input | Boot-mode select sampled at reset: high selects ISP programming mode, low selects user mode executing Flash code with SWD programming available. |
| 45 | PB08 | bidirectional | GPIO with alternate functions I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, TIM3_CH2A and UART0_TXD. |
| 46 | PB09 | bidirectional | GPIO with alternate functions I2C0_SDA, IR_OUT, SPI1_CS, TIM2_CHA, TIM2_CHB and UART0_RXD. |
| 47 | DVSS | power_in | Digital ground, which must be connected to the external supply system within the allowed range. |
| 48 | DVCC | power_in | Digital supply, which must be the same voltage as AVCC (1.8 to 5.5 V operating range) and needs its own decoupling capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage VCC-VSS (incl. AVCC and DVCC) | VCC - VSS | -0.3 | 5.5 | V | 49 | ||
| Voltage difference between supply pins | /ΔVCCx/ | 50 | mV | 49 | |||
| Voltage difference between ground pins | /VSSx - VSS/ | 50 | mV | 49 | |||
| Total current through DVCC/AVCC supply lines (supply current) | IVCC | 300 | mA | 49 | |||
| Total current through VSS ground line (sink current) | IVSS | 300 | mA | 49 | |||
| Output sink current on any I/O and control pin | IIO | 25 | mA | 49 | |||
| Output current on any I/O and control pin (source) | IIO | -25 | mA | 49 | |||
| Injection current on RESETB pin | IINJ(PIN) | -5 | 5 | mA | 49 | ||
| Injection current on XTHI (XTH) and XTLI (XTL) pins | IINJ(PIN) | -5 | 5 | mA | 49 | ||
| Injection current on other pins | IINJ(PIN) | -5 | 5 | mA | 49 | ||
| Total injection current on all I/O and control pins | ∑IINJ(PIN) | -25 | 25 | mA | 49 | ||
| External input voltage range (LVD) | Vex | 0 | V | 53 | |||
| Internal 2.5V reference voltage | VREF25 | 2.475 | 2.5 | 2.525 | V | 常温25°C 3.3V | 54 |
| Internal 2.5V reference voltage | VREF25 | 2.463 | 2.5 | 2.525 | V | -40 |
54 |
| Internal 1.5V reference voltage | VREF15 | 1.485 | 1.5 | 1.515 | V | 常温25°C 3.3V | 54 |
| Internal 1.5V reference voltage | VREF15 | 1.477 | 1.5 | 1.519 | V | -40 |
54 |
| LVD detection threshold tolerance | Vlevel | -3.5 | 3.5 | % | Applies to all LVD_CR.VTDS settings (1.8 to 3.3 V) | 53 | |
| Supply current, run while(1) in Flash, all peripherals ON, RCH clock 4M | IDD | 1000 | 1430 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, RCH clock 8M | IDD | 1890 | 2710 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, RCH clock 16M | IDD | 3710 | 5160 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, RCH clock 22.12M | IDD | 5010 | 7000 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, RCH clock 24M | IDD | 5400 | 7570 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH4M 16M | IDD | 3930 | 4990 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH4M 24M | IDD | 5480 | 7080 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH4M 32M | IDD | 6590 | 7640 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH4M 40M | IDD | 8100 | 9470 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH4M 48M | IDD | 9610 | 11200 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH8M 16M | IDD | 3990 | 5030 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH8M 24M | IDD | 5530 | 7130 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH8M 32M | IDD | 6640 | 7680 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH8M 40M | IDD | 8160 | 9470 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals ON, PLL from RCH8M 48M | IDD | 9670 | 11240 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, RCH clock 4M | IDD | 610 | 990 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, RCH clock 8M | IDD | 1090 | 1830 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, RCH clock 16M | IDD | 2080 | 3350 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, RCH clock 22.12M | IDD | 2770 | 4480 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, RCH clock 24M | IDD | 2970 | 4810 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, PLL from RCH4M 16M | IDD | 2290 | 3150 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, PLL from RCH4M 24M | IDD | 3060 | 4360 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, PLL from RCH4M 32M | IDD | 3410 | 4020 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| Supply current, run while(1) in Flash, all peripherals OFF, PLL from RCH4M 40M | IDD | 4110 | 4950 | μA | VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C, FlashWait=1 | 55 | |
| LVD detection threshold (VTDS=0000) | Vlevel | 1.8 | V | LVD_CR.VTDS=0000 | 53 | ||
| LVD detection threshold (VTDS=0001) | Vlevel | 1.9 | V | LVD_CR.VTDS=0001 | 53 | ||
| LVD detection threshold (VTDS=0010) | Vlevel | 2 | V | LVD_CR.VTDS=0010 | 53 | ||
| LVD detection threshold (VTDS=0011) | Vlevel | 2.1 | V | LVD_CR.VTDS=0011 | 53 | ||
| LVD detection threshold (VTDS=0100) | Vlevel | 2.2 | V | LVD_CR.VTDS=0100 | 53 | ||
| LVD detection threshold (VTDS=0101) | Vlevel | 2.3 | V | LVD_CR.VTDS=0101 | 53 | ||
| LVD detection threshold (VTDS=0110) | Vlevel | 2.4 | V | LVD_CR.VTDS=0110 | 53 | ||
| LVD detection threshold (VTDS=0111) | Vlevel | 2.5 | V | LVD_CR.VTDS=0111 | 53 | ||
| LVD detection threshold (VTDS=1000) | Vlevel | 2.6 | V | LVD_CR.VTDS=1000 | 53 | ||
| LVD detection threshold (VTDS=1001) | Vlevel | 2.7 | V | LVD_CR.VTDS=1001 | 53 | ||
| LVD detection threshold (VTDS=1010) | Vlevel | 2.8 | V | LVD_CR.VTDS=1010 | 53 | ||
| LVD detection threshold (VTDS=1011) | Vlevel | 2.9 | V | LVD_CR.VTDS=1011 | 53 | ||
| LVD detection threshold (VTDS=1100) | Vlevel | 3 | V | LVD_CR.VTDS=1100 | 53 | ||
| LVD detection threshold (VTDS=1101) | Vlevel | 3.1 | V | LVD_CR.VTDS=1101 | 53 | ||
| LVD detection threshold (VTDS=1110) | Vlevel | 3.2 | V | LVD_CR.VTDS=1110 | 53 | ||
| LVD detection threshold (VTDS=1111) | Vlevel | 3.3 | V | LVD_CR.VTDS=1111 | 53 |
CAD (KiCad official)
- Symbol:
HC32L190JCTA-LQ48 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
hc32l190jcta-lq48-etched.step/hc32l190jcta-lq48-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32l190jcta-lq48.step/hc32l190jcta-lq48.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (98 pp, sha256
3664a76916c1dfdf, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).