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HC32L170JATA-LQ48

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllershc32l170jata-lq48factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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HC32L170JATA-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32L170JATA-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCAP power_out Internal LDO core-supply output for internal circuits only, requiring an external decoupling capacitor of not less than 1 uF.
2 PC13 bidirectional GPIO PC13 with RTC_1HZ and TIM3_CH1B digital alternates and LVD0 as a low-voltage-detect monitor input.
3 XTLI/PC14 passive Low-speed crystal oscillator input (XTL, 32.768 kHz) whose load capacitance must follow the crystal maker's specification; PC14 is also a GPIO.
4 XTLO/PC15 passive Low-speed crystal oscillator output (XTL, 32.768 kHz) whose load capacitance must follow the crystal maker's specification; PC15 is also a GPIO.
5 XTHI/PF00 passive High-speed crystal oscillator input (XTH, 4-32 MHz); PF00 is also a GPIO with I2C0_SDA and UART1_TXD alternates.
6 XTHO/PF01 passive High-speed crystal oscillator output (XTH, 4-32 MHz); PF01 is also a GPIO with I2C0_SCL, TIM4_CHB and UART1_RXD alternates.
7 RESETB input Reset input with an always-connected internal pull-up of about 80 kOhm, VIL max 0.3VCC and VIH min 0.7VCC; filter pulse 100 ns and non-filter pulse 300 ns.
8 AVSS power_in Analog ground, with a VSS-to-VSS ground difference limited to 50 mV.
9 AVCC power_in Analog supply, which must be at the same voltage as DVCC within the 50 mV limit and within the 1.8-5.5 V operating range.
10 PA00 bidirectional GPIO PA00 with digital alternates (UART1_CTS, LPUART1_TXD, TIM0_ETR, VC0_OUT, TIM1_CHA, TIM3_ETR, TIM0_CHA) and analog inputs AIN0, VC0_INP4, VC0_INN0, VC1_INP0, VC1_INN4.
11 PA01 bidirectional GPIO PA01 with digital alternates (UART1_RTS, LPUART1_RXD, TIM0_CHB, TIM1_ETR, TIM1_CHB, HCLK_OUT, SPI1_MOSI) and analog inputs AIN1, VC0_INP5, VC0_INN1, VC1_INP1, VC1_INN5.
12 PA02 bidirectional GPIO PA02 with digital alternates (UART1_TXD, TIM0_CHA, VC1_OUT, TIM1_CHA, TIM2_CHA, PCLK_OUT, SPI1_MISO) and analog inputs AIN2, VC0_INP6, VC0_INN2, VC1_INP2.
13 PA03 bidirectional GPIO PA03 with digital alternates (UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A, TIM5_CHA) and analog inputs AIN3, VC0_INP7, VC0_INN3, VC1_INP3.
14 PA04 bidirectional GPIO PA04 with digital alternates (SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT, TIM3_CH2B) and analog inputs AIN4, VC0_INP8, VC0_INN4, VC1_INP4, DAC_OUT and OPA_OUT0.
15 PA05 bidirectional GPIO PA05 with digital alternates SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT and XTH_OUT.
16 PA06 bidirectional GPIO PA06 with digital alternates SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT, TIM3_GATE and LPUART0_CTS.
17 PA07 bidirectional GPIO PA07 with digital alternates SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT and TIM4_CHB.
18 PB00 bidirectional GPIO PB00 with digital alternates PCA_CH2, TIM3_CH1B, LPUART0_TXD, TIM5_CHB, RCH_OUT, RCL_OUT and PLL_OUT.
19 PB01 bidirectional GPIO PB01 with digital alternates PCA_CH3, PCLK_OUT, TIM3_CH2B, TIM6_CHB, LPUART0_RTS, VC2_OUT and TCLK_OUT.
20 PB02 bidirectional GPIO PB02 with digital alternates LPTIM_TOG, PCA_ECI, LPUART1_TXD, TIM4_CHA, TIM1_BK, TIM0_BK and TIM2_BK.
21 PB10 bidirectional GPIO PB10 with digital alternates I2C1_SCL, SPI1_SCK, TIM1_CHA, LPUART0_TXD, TIM3_CH1A, LPUART1_RTS and UART1_RTS.
22 PB11 bidirectional GPIO PB11 with digital alternates I2C1_SDA, TIM1_CHB, LPUART0_RXD, TIM2_GATE, TIM6_CHA, LPUART1_CTS and UART1_CTS.
23 DVSS power_in Digital ground, which must be connected to the system ground.
24 DVCC power_in Digital supply, 1.8-5.5 V, which must be at the same voltage as AVCC.
25 PB12 bidirectional GPIO PB12 with digital alternates SPI1_CS, TIM3_BK, LPUART0_TXD, TIM0_BK, LPUART0_RTS and TIM6_CHA.
26 PB13 bidirectional GPIO PB13 with digital alternates SPI1_SCK, I2C1_SCL, TIM3_CH0B, LPUART0_CTS, TIM1_CHA, TIM1_GATE and TIM6_CHB.
27 PB14 bidirectional GPIO PB14 with digital alternates SPI1_MISO, I2C1_SDA, TIM3_CH1B, TIM0_CHA, RTC_1HZ, LPUART0_RTS and TIM1_BK.
28 PB15 bidirectional GPIO PB15 with digital alternates SPI1_MOSI, TIM3_CH2B, TIM0_CHB, TIM0_GATE and LPUART1_RXD.
29 PA08 bidirectional GPIO PA08 with digital alternates UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA and TIM3_BK.
30 PA09 bidirectional GPIO PA09 with digital alternates UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT and TIM5_CHA.
31 PA10 bidirectional GPIO PA10 with digital alternates UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT and TIM6_CHA.
32 PA11 bidirectional GPIO PA11 with digital alternates UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO and TIM4_CHB.
33 PA12 bidirectional GPIO PA12 with digital alternates UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT, SPI0_MOSI and PCNT_S0.
34 PA13/SWDIO bidirectional SWD debug data I/O (SWDIO) shared with GPIO PA13, which also carries IR_OUT, UART0_RXD, LVD_OUT, TIM3_ETR, RTC_1HZ, PCNT_S1 and VC2_OUT alternates.
35 PF06 bidirectional GPIO PF06 with digital alternates I2C1_SCL, LPUART1_CTS and UART0_CTS.
36 PF07 bidirectional GPIO PF07 with digital alternates I2C1_SDA, LPUART1_RTS and UART0_RTS.
37 PA14/SWCLK input SWD debug clock (SWCLK) shared with GPIO PA14, which also carries UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT and PLL_OUT alternates.
38 PA15 bidirectional GPIO PA15 with digital alternates SPI0_CS, UART1_RXD, LPUART1_RTS, TIM0_ETR, TIM0_CHA and TIM3_CH1A.
39 PB03 bidirectional GPIO PB03 with digital alternates SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, LPTIM_GATE, XTL_OUT and XTH_OUT.
40 PB04 bidirectional GPIO PB04 with digital alternates SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B and LPTIM_ETR.
41 PB05 bidirectional GPIO PB05 with digital alternates SPI0_MOSI, TIM1_BK, PCA_CH1, LPTIM_GATE, PCNT_S0 and UART0_RTS.
42 PB06 bidirectional GPIO PB06 with digital alternates I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA, LPTIM_ETR, TIM3_CH0A and LPTIM_TOG.
43 PB07 bidirectional GPIO PB07 with digital alternates I2C0_SDA, UART0_RXD, TIM2_CHB, LPUART1_CTS, TIM0_CHB, LPTIM_TOGN and PCNT_S1.
44 BOOT0 input Boot-mode select sampled at reset (PF11): high selects ISP programming mode, low selects user mode running Flash code with SWD access.
45 PB08 bidirectional GPIO PB08 with digital alternates I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, TIM3_CH2A and UART0_TXD.
46 PB09 bidirectional GPIO PB09 with digital alternates I2C0_SDA, IR_OUT, SPI1_CS, TIM2_CHA, TIM2_CHB and UART0_RXD.
47 DVSS power_in Digital ground, which must be connected to the system ground.
48 DVCC power_in Digital supply, 1.8-5.5 V, which must be at the same voltage as AVCC.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC-VSS (incl. AVCC and DVCC) VCC-VSS -0.3 5.5 V external main supply 49
Input voltage on any other pin VIN -0.3 V min is VSS-0.3; max is VCC+0.3 (not numeric); referenced to VSS 49
Voltage difference between supply pins /ΔVCCx/ 50 mV 49
Voltage difference between ground pins /VSSx - VSS/ 50 mV 49
Total current through DVCC/AVCC supply lines IVCC 300 mA supply current 49
Total current through VSS ground lines IVSS 300 mA sink current 49
Output sink current on any I/O and control pin IIO 25 mA 49
Output source current on any I/O and control pin IIO -25 mA 49
Injection current on RESETB pin IINJ(PIN) -5 5 mA RESETB pin 49
Injection current on XTHI and XTLI pins IINJ(PIN) -5 5 mA XTHI pin of XTH and XTLI pin of XTL 49
Injection current on other pins IINJ(PIN) -5 5 mA other pins 49
Total injection current on all I/O and control pins ΣIINJ(PIN) -25 25 mA all I/O and control pins 49
External input voltage range Vex 0 V max is VCC (not numeric) 53
LVD detection threshold tolerance Vlevel -3.5 3.5 % LVD_CR.VTDS 0000 to 1111 (1.8 to 3.3 V settings) 53
LVD power consumption Icomp 0.12 μA 53
LVD response time Tresponse 80 μs 53
LVD setup time Tsetup 400 μs 53
LVD hysteresis voltage Vhyste 40 mV 53
LVD filter time Tfilter 7 28800 μs LVD_debounce = 000 to 111 53
Internal 2.5V reference voltage VREF25 2.475 2.5 2.525 V 25°C, VCC 3.3V 54
Internal 2.5V reference voltage VREF25 2.463 2.5 2.525 V -40 ~ 85°C, VCC 2.8~5.5V 54
Internal 1.5V reference voltage VREF15 1.485 1.5 1.515 V 25°C, VCC 3.3V 54
Internal 1.5V reference voltage VREF15 1.477 1.5 1.519 V -40 ~ 85°C, VCC 1.8~5.5V 54
Internal 2.5V / 1.5V reference temperature coefficient TCoeff 120 ppm/°C -40 ~ 85°C 54
IDD run in RAM, all peripherals on, RCH clock 4M IDD 750 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC 54
IDD run in RAM, all peripherals on, RCH clock 8M IDD 1460 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC 54
IDD run in RAM, all peripherals on, RCH clock 16M IDD 2850 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC 54
IDD run in RAM, all peripherals on, RCH clock 22.12M IDD 3940 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC 54
IDD run in RAM, all peripherals on, RCH clock 24M IDD 4270 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC 54
IDD run in RAM, all peripherals on, PLL 48M IDD 8540 μA run while(1) in RAM, VCAP=1.5V, VCC=3.3V, TA=2xC, PLL from RCH4M 54
IDD run in Flash, all peripherals on, RCH clock 4M IDD 1000 1430 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, RCH clock 8M IDD 1890 2710 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, RCH clock 16M IDD 3710 5160 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, RCH clock 22.12M IDD 5010 7000 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, RCH clock 24M IDD 5400 7570 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH4M 16M IDD 3930 4990 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH4M 24M IDD 5480 7080 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH4M 32M IDD 6590 7640 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH4M 40M IDD 8100 9470 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH4M 48M IDD 9610 11200 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH8M 16M IDD 3990 5030 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH8M 24M IDD 5530 7130 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH8M 32M IDD 6640 7680 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH8M 40M IDD 8160 9470 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD run in Flash, all peripherals on, PLL from RCH8M 48M IDD 9670 11240 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, RCH clock 4M IDD 610 990 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, RCH clock 8M IDD 1090 1830 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, RCH clock 16M IDD 2080 3350 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, RCH clock 22.12M IDD 2770 4480 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, RCH clock 24M IDD 2970 4810 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, PLL from RCH4M 16M IDD 2290 3150 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, PLL from RCH4M 24M IDD 3060 4360 μA run while(1) in Flash, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, PLL from RCH4M 32M IDD 3410 4020 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD sleep in Flash, all peripherals off, PLL from RCH4M 40M IDD 4110 4950 μA run while(1) in Flash, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55

CAD (KiCad official)

  • Symbol: HC32L170JATA-LQ48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hc32l170jata-lq48-etched.step / hc32l170jata-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32l170jata-lq48.step / hc32l170jata-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (98 pp, sha256 566056c166174c9d, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF