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HC32F4A0PITB-LQFP100

Public Made by Adom

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllershc32f4a0pitb-lqfp100factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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HC32F4A0PITB-LQFP100

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

HC32F4A0PITB-LQFP100 from XHSC, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO PE2, 5 V tolerant (Table 2-4); EIRQ2 external interrupt and TRACECLK trace clock output are multiplexed on this pin.
2 PE3 bidirectional GPIO PE3, 5 V tolerant (Table 2-4); EIRQ3 external interrupt and TRACED0 trace data output are multiplexed on this pin.
3 PE4 bidirectional GPIO PE4, 5 V tolerant (Table 2-4); EIRQ4 external interrupt and TRACED1 trace data output are multiplexed on this pin.
4 PE5 bidirectional GPIO PE5, 5 V tolerant (Table 2-4); EIRQ5 external interrupt and TRACED2 trace data output are multiplexed on this pin.
5 PE6 bidirectional GPIO PE6, 5 V tolerant (Table 2-4); EIRQ6 external interrupt and TRACED3 trace data output are multiplexed on this pin.
6 VBAT power_in Backup battery supply, 1.65 V to 3.6 V (Table 3-5); if unused, short to VCC and add 100 nF decoupling (Section 2.4).
7 PC13 bidirectional GPIO PC13 with RTCIC0 RTC time-stamp input; combined sink/source current of PC13, PC14, PC15 and PI8 must not exceed 20 mA (Section 3.3.11).
8 PC14 bidirectional GPIO PC14 with XTAL32_OUT low-speed oscillator output; combined sink/source current of PC13, PC14, PC15 and PI8 must not exceed 20 mA (Section 3.3.11).
9 PC15 bidirectional GPIO PC15 with XTAL32_IN low-speed oscillator input (32.768 kHz crystal); combined PC13/PC14/PC15/PI8 current must not exceed 20 mA (Section 3.3.11).
10 VSS power_in Ground reference, 0 V (Section 2.4).
11 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple close to VSS (Section 2.4, Table 3-5).
12 PH0 bidirectional GPIO PH0 with XTAL_IN high-speed external oscillator input for a 4 to 25 MHz crystal or resonator (Table 3-18).
13 PH1 bidirectional GPIO PH1 with XTAL_OUT high-speed external oscillator output for a 4 to 25 MHz crystal or resonator (Table 3-18).
14 NRST input Active-low reset input; pull up to VCC through a resistor when unused, and the low pulse must be at least 10 µs (Section 2.4, Table 3-7).
15 PC0 bidirectional GPIO PC0 with ADC123_IN10 analog input and CMP3_INP4 comparator input; analog voltage must not exceed VREFH/AVCC (Section 2.4).
16 PC1 bidirectional GPIO PC1 with ADC123_IN11 analog input; analog voltage must not exceed VREFH/AVCC (Section 2.4).
17 PC2 bidirectional GPIO PC2 with ADC123_IN12 analog input; analog voltage must not exceed VREFH/AVCC (Section 2.4).
18 PC3 bidirectional GPIO PC3 with ADC123_IN13 analog input and CMP1_INM4 comparator negative input; analog voltage must not exceed VREFH/AVCC (Section 2.4).
19 VCC power_in Digital supply, 1.8 V to 3.6 V (Table 3-5).
20 AVSS_VREFL power_in Analog ground shared with the VREFL reference; connect to the same voltage as VSS (Section 2.4).
21 VREFH power_in ADC/DAC high reference voltage, must not exceed AVCC (Section 2.4); tie to AVCC when the ADC is unused.
22 AVCC power_in Analog supply, 1.8 V to 3.6 V (Table 3-5); tie to VCC when analog modules are unused (Section 2.4).
23 PA0 bidirectional GPIO PA0, not 5 V tolerant (Table 2-4); ADC123_IN0 / PGA_1 / SH_1 analog input, input must not exceed VCC.
24 PA1 bidirectional GPIO PA1, not 5 V tolerant (Table 2-4); ADC123_IN1 / PGA_2 / SH_2 analog input, input must not exceed VCC.
25 PA2 bidirectional GPIO PA2, not 5 V tolerant (Table 2-4); ADC123_IN2 / PGA_3 / SH_3 analog input, input must not exceed VCC.
26 PA3 bidirectional GPIO PA3, 5 V tolerant (Table 2-4); ADC123_IN3 / PGA123_VSS / CMP1_INP4 analog input.
27 AVSS power_in Analog ground; connect to the same voltage as VSS (Section 2.4).
28 AVCC power_in Analog supply, 1.8 V to 3.6 V (Table 3-5).
29 PA4 bidirectional GPIO PA4, 5 V tolerant (Table 2-4); ADC12_IN4 analog input, DAC1_OUT1 DAC output and CMP2_INP3 comparator input.
30 PA5 bidirectional GPIO PA5, 5 V tolerant (Table 2-4); ADC12_IN5 analog input, DAC1_OUT2 DAC output and CMP2_INP4 comparator input.
31 PA6 bidirectional GPIO PA6, not 5 V tolerant (Table 2-4); ADC12_IN6, PGA_4 and CMP1_INP2 analog inputs.
32 PA7 bidirectional GPIO PA7, 5 V tolerant (Table 2-4); ADC12_IN7 analog input, PGA4_VSS ground input and CMP123_INM3 comparator input.
33 PC4 bidirectional GPIO PC4, 5 V tolerant (Table 2-4); ADC12_IN14 analog input, DAC2_OUT1 DAC output and CMP2_INM4 comparator input.
34 PC5 bidirectional GPIO PC5, 5 V tolerant (Table 2-4); ADC12_IN15 analog input, DAC2_OUT2 DAC output and CMP3_INM4 comparator input.
35 PB0 bidirectional GPIO PB0, 5 V tolerant (Table 2-4); ADC12_IN8 analog input and CMP3_INP2 comparator input, with EIRQ0 multiplexed.
36 PB1 bidirectional GPIO PB1, 5 V tolerant (Table 2-4); ADC12_IN9 analog input and CMP3_INP3 comparator input, with EIRQ1/WKUP0_1 multiplexed.
37 PB2 bidirectional GPIO PB2, 5 V tolerant (Table 2-4); PVD2EXINP external comparison input for PVD2, with EIRQ2/WKUP0_2 and VCOUT multiplexed.
38 PE7 bidirectional GPIO PE7, 5 V tolerant (Table 2-4); EIRQ7 external interrupt and ADTRG1 ADC external trigger, with EXMC_DATA4 multiplexed.
39 PE8 bidirectional GPIO PE8, 5 V tolerant (Table 2-4); EIRQ8 external interrupt and CTCREF reference input, with EXMC_DATA5 multiplexed.
40 PE9 bidirectional GPIO PE9, 5 V tolerant (Table 2-4); EIRQ9 external interrupt and ADTRG3 ADC external trigger, with EXMC_DATA6 multiplexed.
41 PE10 bidirectional GPIO PE10, 5 V tolerant (Table 2-4); CMP1_INP3 comparator input, with EIRQ10 and EXMC_DATA7 multiplexed.
42 PE11 bidirectional GPIO PE11, 5 V tolerant (Table 2-4); EIRQ11 external interrupt, with USBHS_ULPI_D7 and EXMC_DATA8 multiplexed.
43 PE12 bidirectional GPIO PE12, 5 V tolerant (Table 2-4); CMP4_INM3 comparator input, with EIRQ12 and EXMC_DATA9 multiplexed.
44 PE13 bidirectional GPIO PE13, 5 V tolerant (Table 2-4); CMP4_INM4 comparator input, with EIRQ13 and EXMC_DATA10 multiplexed.
45 PE14 bidirectional GPIO PE14, 5 V tolerant (Table 2-4); CMP4_INP3 comparator input, with EIRQ14 and EXMC_DATA11 multiplexed.
46 PE15 bidirectional GPIO PE15, 5 V tolerant (Table 2-4); CMP4_INP4 comparator input, with EIRQ15 and EXMC_DATA12 multiplexed.
47 PB10 bidirectional GPIO PB10, 5 V tolerant (Table 2-4); EIRQ10 external interrupt and ADTRG2 ADC external trigger, with QSPI_IO2 multiplexed.
48 PB11 bidirectional GPIO PB11, 5 V tolerant (Table 2-4); EIRQ11 external interrupt, with USBHS_ULPI_D4 and ETH_MII_RMII_TXEN multiplexed.
49 VCAP_1 power_out Core voltage (internal regulator) decoupling; use 0.047 µF or 0.1 µF with ESR below 0.3 Ω, and the VCAP total must match PWC_PWRC3.PDTS (Section 3.1.6, Table 3-1).
50 VCC power_in Digital supply, 1.8 V to 3.6 V (Table 3-5).
51 PB12 bidirectional GPIO PB12, 5 V tolerant (Table 2-4); EIRQ12 external interrupt and VCOUT1 comparator output, with USBHS_ULPI_D5 multiplexed.
52 PB13 bidirectional GPIO PB13, 5 V tolerant (Table 2-4); EIRQ13 external interrupt and VCOUT2 comparator output, with USBHS_ULPI_D6 multiplexed.
53 PB14 bidirectional GPIO PB14, not 5 V tolerant (Table 2-4); USBHS_DM high-speed USB D- signal, with EIRQ14 and VCOUT3 multiplexed.
54 PB15 bidirectional GPIO PB15, not 5 V tolerant (Table 2-4); USBHS_DP high-speed USB D+ signal, with EIRQ15 and RTC_OUT multiplexed.
55 PD8 bidirectional GPIO PD8, 5 V tolerant (Table 2-4); EIRQ8 external interrupt and VCOUT4 comparator output, with USBHS_DRVVBUS and EXMC_DATA13 multiplexed.
56 PD9 bidirectional GPIO PD9, 5 V tolerant (Table 2-4); EIRQ9 external interrupt and VCOUT3 comparator output, with EXMC_DATA14 multiplexed.
57 PD10 bidirectional GPIO PD10, 5 V tolerant (Table 2-4); EIRQ10 external interrupt and CAN2_TST_SAMPLE, with EXMC_DATA15 multiplexed.
58 PD11 bidirectional GPIO PD11, 5 V tolerant (Table 2-4); EIRQ11 external interrupt and CAN2_TST_CLOCK, with EXMC_ADD16 multiplexed.
59 PD12 bidirectional GPIO PD12, 5 V tolerant (Table 2-4); EIRQ12 external interrupt, with EXMC_ADD17 multiplexed.
60 PD13 bidirectional GPIO PD13, 5 V tolerant (Table 2-4); EIRQ13 external interrupt, with EXMC_ADD18 multiplexed.
61 PD14 bidirectional GPIO PD14, 5 V tolerant (Table 2-4); EIRQ14 external interrupt and ADTRG1 ADC external trigger, with EXMC_DATA0 multiplexed.
62 PD15 bidirectional GPIO PD15, 5 V tolerant (Table 2-4); EIRQ15 external interrupt and ADTRG2 ADC external trigger, with EXMC_DATA1 multiplexed.
63 PC6 bidirectional GPIO PC6, 5 V tolerant (Table 2-4); EIRQ6 external interrupt and CTCREF reference input, with I2S1_MCK and SDIO1_D6 multiplexed.
64 PC7 bidirectional GPIO PC7, 5 V tolerant (Table 2-4); EIRQ7 external interrupt, with I2S2_MCK and USART6_RX multiplexed.
65 PC8 bidirectional GPIO PC8, 5 V tolerant (Table 2-4); EIRQ8 external interrupt, with KEYOUT1 and USART6_CK multiplexed.
66 PC9 bidirectional GPIO PC9, 5 V tolerant (Table 2-4); EIRQ9 external interrupt and MCO_2 clock output, with KEYOUT0 multiplexed.
67 PA8 bidirectional GPIO PA8, 5 V tolerant (Table 2-4); EIRQ8 / WKUP2_0 wake-up input and MCO_1 clock output, with USART1_CK multiplexed.
68 PA9 bidirectional GPIO PA9, 5 V tolerant (Table 2-4); EIRQ9 / WKUP2_1 wake-up input, with USART1_TX multiplexed.
69 PA10 bidirectional GPIO PA10, 5 V tolerant (Table 2-4); EIRQ10 / WKUP2_2 wake-up input, with USART1_RX multiplexed.
70 PA11 bidirectional GPIO PA11, not 5 V tolerant (Table 2-4); USBFS_DM full-speed USB D- signal, with EIRQ11 / WKUP2_3 multiplexed.
71 PA12 bidirectional GPIO PA12, not 5 V tolerant (Table 2-4); USBFS_DP full-speed USB D+ signal, with EIRQ12 / WKUP3_0 multiplexed.
72 PA13 bidirectional GPIO PA13, 5 V tolerant (Table 2-4); JTMS_SWDIO debug data pin, with EIRQ13 multiplexed.
73 VCAP_2 power_out Core voltage (internal regulator) decoupling; use 0.047 µF or 0.1 µF with ESR below 0.3 Ω, and the VCAP total must match PWC_PWRC3.PDTS (Section 3.1.6, Table 3-1).
74 VSS power_in Ground reference, 0 V (Section 2.4).
75 VCC power_in Digital supply, 1.8 V to 3.6 V (Table 3-5).
76 PA14 bidirectional GPIO PA14, 5 V tolerant (Table 2-4); JTCK_SWCLK debug clock pin, with EIRQ14 / WKUP3_2 multiplexed.
77 PA15 bidirectional GPIO PA15, 5 V tolerant (Table 2-4); JTDI JTAG data input, with EIRQ15 / WKUP3_3 multiplexed.
78 PC10 bidirectional GPIO PC10, 5 V tolerant (Table 2-4); EIRQ10 external interrupt and CAN1_TST_SAMPLE, with DVP_DATA8 multiplexed.
79 PC11 bidirectional GPIO PC11, 5 V tolerant (Table 2-4); EIRQ11 external interrupt and CAN1_TST_CLOCK, with DVP_DATA4 multiplexed.
80 PC12 bidirectional GPIO PC12, 5 V tolerant (Table 2-4); EIRQ12 external interrupt, with USART3_CK and SDIO1_CK multiplexed.
81 PD0 bidirectional GPIO PD0, 5 V tolerant (Table 2-4); EIRQ0 external interrupt and VCOUT comparator OR output, with EXMC_DATA2 multiplexed.
82 PD1 bidirectional GPIO PD1, 5 V tolerant (Table 2-4); EIRQ1 external interrupt, with EXMC_DATA3 multiplexed.
83 PD2 bidirectional GPIO PD2, 5 V tolerant (Table 2-4); EIRQ2 external interrupt and VCOUT4 comparator output, with SDIO1_CMD multiplexed.
84 PD3 bidirectional GPIO PD3, 5 V tolerant (Table 2-4); EIRQ3 external interrupt and VCOUT1 comparator output, with EXMC_CLK multiplexed.
85 PD4 bidirectional GPIO PD4, 5 V tolerant (Table 2-4); EIRQ4 external interrupt and VCOUT2 comparator output, with EXMC_OE multiplexed.
86 PD5 bidirectional GPIO PD5, 5 V tolerant (Table 2-4); EIRQ5 external interrupt and VCOUT3 comparator output, with EXMC_WE multiplexed.
87 PD6 bidirectional GPIO PD6, 5 V tolerant (Table 2-4); EIRQ6 external interrupt and ADTRG1 ADC external trigger, with EXMC_RB0 multiplexed.
88 PD7 bidirectional GPIO PD7, 5 V tolerant (Table 2-4); EIRQ7 external interrupt and ADTRG2 ADC external trigger, with EXMC_CE0 multiplexed.
89 PB3 bidirectional GPIO PB3, 5 V tolerant (Table 2-4); JTDO_TRACESWO debug/trace output, with EIRQ3 / WKUP0_3 and FCMREF multiplexed.
90 PB4 bidirectional GPIO PB4, 5 V tolerant (Table 2-4); NJTRST JTAG reset input, with EIRQ4 / WKUP1_0 multiplexed.
91 PB5 bidirectional GPIO PB5, 5 V tolerant (Table 2-4); EIRQ5 / WKUP1_1 wake-up input and ADTRG3 ADC external trigger, with USBHS_ULPI_D7 multiplexed.
92 PB6 bidirectional GPIO PB6, 5 V tolerant (Table 2-4); EIRQ6 / WKUP1_2 wake-up input and ADTRG2 ADC external trigger, with ETH_MII_TXCLK multiplexed.
93 PB7 bidirectional GPIO PB7, 5 V tolerant (Table 2-4); EIRQ7 / WKUP1_3 wake-up input and ADTRG1 ADC external trigger, with DVP_VSYNC multiplexed.
94 PI13/MD bidirectional GPIO PI13 shared with the MD mode input; MD must be held low when NRST is released, and a 4.7 kΩ pull-down to VSS is recommended (Section 2.4).
95 PB8 bidirectional GPIO PB8, 5 V tolerant (Table 2-4); EIRQ8 external interrupt and KEYOUT7, with USBFS_DRVVBUS multiplexed.
96 PB9 bidirectional GPIO PB9, 5 V tolerant (Table 2-4); EIRQ9 external interrupt and KEYOUT6, with SDIO1_D5 multiplexed.
97 PE0 bidirectional GPIO PE0, 5 V tolerant (Table 2-4); EIRQ0 external interrupt and MCO_1 clock output, with DVP_DATA2 multiplexed.
98 PE1 bidirectional GPIO PE1, 5 V tolerant (Table 2-4); EIRQ1 external interrupt and MCO_2 clock output, with DVP_DATA3 multiplexed.
99 VSS power_in Ground reference, 0 V (Section 2.4).
100 VCC power_in Digital supply, 1.8 V to 3.6 V (Table 3-5).

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
System supply voltage (Vcc) VCC 1.8 3.6 V 2
I/O input leakage current ILKG 1 µA VSS≤VIN≤VCC 87
I/O input leakage current ILKG 10 µA VIN = 5.5V 87
I/O pin capacitance (USB pins) CIO 10 pF PA11/USBFS_DM, PA12/USBFS_DP, PB14/USBHS_DM, PB15/USBHS_DP 87
I/O pin capacitance (other input pins) CIO 5 pF Input pins other than the USB pins above 87
Low-level output voltage, low drive VOL 0.6 V Low drive; IIO=1.5mA, 1.8≤VCC<2.7 89
Low-level output voltage, low drive VOL 1.3 V Low drive; IIO=6mA, 2.7≤VCC≤3.6 89
Low-level output voltage, medium drive VOL 0.4 V Medium drive; IIO=3mA, 1.8≤VCC<2.7 89
Low-level output voltage, medium drive VOL 1.3 V Medium drive; IIO=12mA, 2.7≤VCC≤3.6 89
Low-level output voltage, high drive VOL 0.4 V High drive; IIO=6mA, 1.8≤VCC<2.7 89
Low-level output voltage, high drive VOL 1.3 V High drive; IIO=20mA, 2.7≤VCC≤3.6 89
GPIO source or sink current IIO 20 mA 89
Sum of source or sink current, PC13/PC14/PC15/PI8 ∑IIO 20 mA PC13、PC14、PC14、PI8 (as printed) 89
USB FS operating voltage VCC 3 3.6 V 100
USB FS input low voltage VIL 0.8 V 100
USB FS input high voltage VIH 2 V 100
USB FS differential input sensitivity VDI 0.2 V 100
USB FS differential common-mode voltage VCM 0.8 2.5 V 100
USB FS static output low voltage VOL 0.3 V RL=1.5kΩ to 3.6V 100
USB FS static output high voltage VOH 2.8 3.6 V RL=15kΩ to VSS 100
USB FS cross-over voltage VCRS 1.3 2 V CL=50pF 100
USB FS rise time tR 4 20 ns CL=50pF, 10%~90% of /VOH-VOL/ 100
USB FS fall time tF 4 20 ns CL=50pF, 10%~90% of /VOH-VOL/ 100
USB FS rise/fall time ratio tRFMA 90 111 % CL=50pF 100
USB FS pull-up resistance, idle state RPU 0.9 1.2 1.575 kΩ VIN=VSS, idle state 100
USB FS pull-up resistance, device mode RPU 1.425 2.3 3.09 kΩ VIN=VSS, in device mode 100
USB FS driver output impedance ZDRV 28 36 44 Ω Driving high or low 100
USB LS operating voltage VCC 3 3.6 V 101
USB LS input low voltage VIL 0.8 V 101
USB LS input high voltage VIH 2 V 101
USB LS differential input sensitivity VDI 0.2 V 101
USB LS differential common-mode voltage VCM 0.8 2.5 V 101
USB LS static output low voltage VOL 0.3 V RL=1.5kΩ to 3.6V 101
USB LS static output high voltage VOH 2.8 3.6 V RL=15kΩ to VSS 101
USB LS cross-over voltage VCRS 1.3 2 V CL=200pF~600pF 101
USB LS rise time tR 75 300 ns CL=200pF~600pF, 10%~90% of /VOH-VOL/ 101
USB LS fall time tF 75 300 ns CL=200pF~600pF, 10%~90% of /VOH-VOL/ 101
USB LS rise/fall time ratio tRFMA 80 125 % CL=200pF~600pF 101
USB LS driver output impedance ZDRV 28 36 44 Ω Driving high or low 101
PGA analog supply voltage VAVCC 1.8 3.3 3.6 V 129
PGA input offset voltage VOS -8 8 Mv 129
ULPI control signal setup time (ULPI_DIR, ULPI_NXT) tSC 3 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 102
ULPI control signal hold time (ULPI_DIR, ULPI_NXT) tHC 2 ns 102
ULPI data setup time tSD 3 ns 102
ULPI data hold time tHD 2.2 ns 102
ULPI data/control output delay tDC/tDD 4.5 7.5 10.6 ns 102
SPI data input setup time, slave mode tsu(SI) 4 ns slave mode, 1.8V≤Vcc≤3.6V 93
SPI data input hold time, slave mode th(SI) 3 ns slave mode, 1.8V≤Vcc≤3.6V 93
SPI data output valid time, slave mode tv(SO) 15 ns slave mode, 2.7V≤Vcc≤3.6V 93
SPI data output valid time, slave mode tv(SO) 26 ns slave mode, 1.8V≤Vcc<2.7V 93
SPI data input setup time, master mode tsu(MI) 5 ns master mode, 2.7V≤Vcc≤3.6V 93
SPI data input setup time, master mode tsu(MI) 9 ns master mode, 1.8V≤Vcc<2.7V 93
SPI data output valid time, master mode tv(MO) 4 ns master mode, 2.7V≤Vcc≤3.6V 93
SPI data output valid time, master mode tv(MO) 9 ns master mode, 1.8V≤Vcc≤2.7V 93
I2C SCL clock frequency, standard mode fSCL 0 100 kHz Standard mode (SM) 92
I2C SCL clock frequency, fast mode fSCL 0 400 kHz Fast mode (FM) 92
QSPI QSPCK clock cycle tQscyc 2 48 thclk 96

CAD (KiCad official)

  • Symbol: HC32F4A0PITB-LQFP100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: hc32f4a0pitb-lqfp100-etched.step / hc32f4a0pitb-lqfp100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f4a0pitb-lqfp100.step / hc32f4a0pitb-lqfp100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (145 pp, sha256 c971eaaaa12f48ef, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF