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HC32F4A0PGTB-LQFP100

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XHSC Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HC32F4A0PGTB-LQFP100

XHSC · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

HC32F4A0PGTB-LQFP100 from XHSC, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO PE2 with EIRQ2, TRACECLK, FCMREF, TIM4_3_ADSM, TIMA_9, USART3_CK, ETH_MII_TXD3, EXMC_ADD23 and I2S3_MCK alternate functions (FG2).
2 PE3 bidirectional GPIO PE3 with EIRQ3, TRACED0, TIMA_9/TIMA_4 PWM, USART6_CK, ETH_MII_RMII_TXEN, EXMC_ADD19, I2S4_SD and SPI2_NSS0 alternate functions (FG2).
3 PE4 bidirectional GPIO PE4 with EIRQ4, TRACED1, TIMA_9_PWM3, TIMA_4_PWM2, USART6_CTS, EXMC_ADD20, DVP_DATA4 and SPI4_NSS0 alternate functions (FG2).
4 PE5 bidirectional GPIO PE5 with EIRQ5, TRACED2, CTCREF, TIMA_9_PWM4, TIMA_4_PWM3, USART6_RTS, EXMC_ADD21 and DVP_DATA6 alternate functions (FG2).
5 PE6 bidirectional GPIO PE6 with EIRQ6, TRACED3, TIMA_4_PWM4, TIMA_9_TRIG, EXMC_ADD22, DVP_DATA7 and TIM2_1_PWMB/TRIGB alternate functions (FG2).
6 VBAT power_in Backup battery supply (1.65 to 3.6 V) for the RTC and backup domain; short to VCC with a 100 nF decoupling capacitor when unused.
7 PC13 bidirectional GPIO PC13 with RTCIC0 timestamp input, EIRQ13/WKUP3_1, RTC_OUT, TIMA_10_PWM4, SDIO2_CK and I2S3_MCK; combined sink/source current of PC13/PC14/PC15/PI8 limited to 20 mA.
8 PC14 bidirectional GPIO PC14 or XTAL32_OUT (32 kHz oscillator output) with EIRQ14 and TIMA_10 alternate functions; shared 20 mA limit with PC13/PC15/PI8.
9 PC15 bidirectional GPIO PC15 or XTAL32_IN (32 kHz oscillator input) with EIRQ15 and TIMA_10 alternate functions; shared 20 mA limit with PC13/PC14/PI8.
10 VSS power_in Digital ground (0 V); decouple close to the paired VCC pin.
11 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple to VSS with nearby capacitors.
12 PH0 bidirectional GPIO PH0 or XTAL_IN (external main oscillator input, 4-25 MHz) with EIRQ0 and TIMA_5_PWM3.
13 PH1 bidirectional GPIO PH1 or XTAL_OUT (external main oscillator output) with EIRQ1 and TIMA_5_PWM4.
14 NRST input Active-low reset input; connect a pull-up resistor to VCC when unused.
15 PC0 bidirectional GPIO PC0 with ADC123_IN10 and CMP3_INP4 analog functions, EIRQ0, SDIO2_D5, USBHS_ULPI_STP, EXMC_WE and I2S1_EXCK (FG3).
16 PC1 bidirectional GPIO PC1 with ADC123_IN11 analog input, EIRQ1, SDIO2_D6, ETH_SMI_MDC and I2S1_MCK (FG3).
17 PC2 bidirectional GPIO PC2 with ADC123_IN12 analog input, EIRQ2, TIM6_8_PWMA, SDIO2_D7, USBHS_ULPI_DIR, ETH_MII_TXD2, EXMC_CE0 and SPI2_MISO (FG3).
18 PC3 bidirectional GPIO PC3 with ADC123_IN13 and CMP1_INM4 analog functions, EIRQ3, SDIO1_WP, USBHS_ULPI_NXT, ETH_MII_TXCLK, EXMC_ALE and SPI2_MOSI (FG3).
19 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple to VSS with nearby capacitors.
20 AVSS_VREFL power_in Analog ground shared with the VREFL reference ground; connect to the same voltage as VSS.
21 VREFH power_in Analog reference voltage high; connect to a voltage not higher than AVCC, or short to AVCC if the ADC is unused.
22 AVCC power_in Analog supply (1.8 V to 3.6 V) at the same voltage as VCC; short to VCC when analog modules are unused.
23 PA0 bidirectional GPIO PA0 with ADC123_IN0 and PGA_1 analog functions, EIRQ0/WKUP0_0, TIM4_2_OUH, TIMA_2/TIMA_5 PWM, SDIO2_D4, USART2_CTS; not 5 V tolerant (FG2).
24 PA1 bidirectional GPIO PA1 with ADC123_IN1 and PGA_2 analog functions, EIRQ1, TIM4_2_OUL, SDIO2_D5, ETH_MII_RMII_RXCLK, USART2_RTS; not 5 V tolerant (FG2).
25 PA2 bidirectional GPIO PA2 with ADC123_IN2 and PGA_3 analog functions, EIRQ2, TIM4_2_OVH, SDIO2_D6, ETH_SMI_MDIO, USART2_TX; not 5 V tolerant (FG2).
26 PA3 bidirectional GPIO PA3 with ADC123_IN3, PGA123_VSS and CMP1_INP4 analog functions, EIRQ3, TIM4_2_OVL, SDIO2_D7, USBHS_ULPI_D0, USART2_RX (FG2).
27 AVSS power_in Analog ground; connect to the same voltage as VSS.
28 AVCC power_in Analog supply (1.8 V to 3.6 V) at the same voltage as VCC; short to VCC when analog modules are unused.
29 PA4 bidirectional GPIO PA4 with ADC12_IN4, DAC1_OUT1 and CMP2_INP3 analog functions, EIRQ4, TIM4_2_OWH, KEYOUT0, USBHS_SOF, DVP_HSYNC, SPI1_NSS0 (FG1).
30 PA5 bidirectional GPIO PA5 with ADC12_IN5, DAC1_OUT2 and CMP2_INP4 analog functions, EIRQ5, TIM4_2_OWL, KEYOUT1, USBHS_ULPI_CK, I2S1_MCK (FG1).
31 PA6 bidirectional GPIO PA6 with ADC12_IN6, PGA_4 and CMP1_INP2 analog functions, EIRQ6, KEYOUT2, SDIO1_CMD, EXMC_ADD26, DVP_PIXCLK; not 5 V tolerant (FG1).
32 PA7 bidirectional GPIO PA7 with ADC12_IN7, PGA4_VSS and CMP123_INM3 analog functions, EIRQ7, TIM4_1_OUL, KEYOUT3, SDIO2_WP, ETH_MII_RMII_RXDV, EXMC_ADD27 (FG1).
33 PC4 bidirectional GPIO PC4 with ADC12_IN14, DAC2_OUT1 and CMP2_INM4 analog functions, EIRQ4, USART1_CK, SDIO2_CD, ETH_MII_RMII_RXD0, EXMC_ADD28 (FG1).
34 PC5 bidirectional GPIO PC5 with ADC12_IN15, DAC2_OUT2 and CMP3_INM4 analog functions, EIRQ5, SDIO2_CMD, ETH_MII_RMII_RXD1, EXMC_ADD29 (FG1).
35 PB0 bidirectional GPIO PB0 with ADC12_IN8 and CMP3_INP2 analog functions, EIRQ0, TIM4_1_OVL, KEYOUT4, SDIO2_CMD, USBHS_ULPI_D1, ETH_MII_RXD2 (FG1).
36 PB1 bidirectional GPIO PB1 with ADC12_IN9 and CMP3_INP3 analog functions, EIRQ1/WKUP0_1, KEYOUT5, SDIO2_D3, USBHS_ULPI_D2, ETH_MII_RXD3, QSPI_NSS (FG1).
37 PB2 bidirectional GPIO PB2 or PVD2EXINP (PVD2 external comparison voltage input) with EIRQ2/WKUP0_2, VCOUT, SDIO2_D2, EXMC_CLE, QSPI_IO3 (FG1).
38 PE7 bidirectional GPIO PE7 with EIRQ7, ADTRG1, TIM4_1_CLK, USART1_CK, EXMC_DATA4 and SPI4_NSS1 alternate functions (FG2).
39 PE8 bidirectional GPIO PE8 with EIRQ8, CTCREF, TIM4_1_OUL, EXMC_DATA5 and SPI4_NSS2 alternate functions (FG2).
40 PE9 bidirectional GPIO PE9 with EIRQ9, ADTRG3, TIM4_1_OUH, EXMC_DATA6 and SPI4_NSS3 alternate functions (FG2).
41 PE10 bidirectional GPIO PE10 with CMP1_INP3 analog input, EIRQ10, TIM4_1_OVL, EXMC_DATA7 (FG3).
42 PE11 bidirectional GPIO PE11 with EIRQ11, TIM4_1_OVH, USBHS_ULPI_D7, EXMC_DATA8 (FG3).
43 PE12 bidirectional GPIO PE12 with CMP4_INM3 analog input, EIRQ12, TIM4_1_OWL, USBHS_ULPI_CK, EXMC_DATA9, SPI1_NSS1 (FG3).
44 PE13 bidirectional GPIO PE13 with CMP4_INM4 analog input, EIRQ13, TIM4_1_OWH, USBHS_ULPI_D0, EXMC_DATA10, I2S4_SDIN (FG3).
45 PE14 bidirectional GPIO PE14 with CMP4_INP3 analog input, EIRQ14, TIM4_1_CLK, SDIO1_CD, USBHS_ULPI_D1, EXMC_DATA11, I2S4_EXCK (FG3).
46 PE15 bidirectional GPIO PE15 with CMP4_INP4 analog input, EIRQ15, TIM4_1_PCT, USART10_CK, SDIO1_WP, USBHS_ULPI_D2, EXMC_DATA12, I2S4_MCK (FG3).
47 PB10 bidirectional GPIO PB10 with EIRQ10, ADTRG2, TIM4_2_OVH, SDIO1_D7, USBHS_ULPI_D3, ETH_MII_RXER, QSPI_IO2, SPI2_SCK (FG3).
48 PB11 bidirectional GPIO PB11 with EIRQ11, TIM4_1_ADSM, EMB_PORT2, USBHS_ULPI_D4, ETH_MII_RMII_TXEN (FG3).
49 VCAP_1 passive Core voltage regulator capacitor pin; connect 0.047 µF or 0.1 µF (ESR < 0.3 Ω) close to VSS.
50 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple to VSS with nearby capacitors.
51 PB12 bidirectional GPIO PB12 with EIRQ12, VCOUT1, TIM4_2_OVL, USART3_CK, SDIO2_D1, USBHS_ULPI_D5, ETH_MII_RMII_TXD0, USBHS_ID, QSPI_IO1, SPI2_NSS0 (FG1).
52 PB13 bidirectional GPIO PB13 with EIRQ13, VCOUT2, TIM4_1_OUL, USART3_CTS, SDIO2_D0, USBHS_ULPI_D6, ETH_MII_RMII_TXD1, USBHS_VBUS, QSPI_IO0 (FG1).
53 PB14 bidirectional GPIO PB14 or USBHS_DM (USB on-chip full-speed PHY D-) with EIRQ14, VCOUT3, USART3_RTS, SDIO1_D6, I2S1_SDIN, QSPI_SCK; not 5 V tolerant (FG1).
54 PB15 bidirectional GPIO PB15 or USBHS_DP (USB on-chip full-speed PHY D+) with EIRQ15, RTC_OUT, USART3_CK, SDIO1_CK; not 5 V tolerant (FG1).
55 PD8 bidirectional GPIO PD8 with EIRQ8, VCOUT4, TIM4_3_OUL, USART1_CTS, KEYOUT7, USBHS_DRVVBUS, EXMC_DATA13, QSPI_IO0 (FG1).
56 PD9 bidirectional GPIO PD9 with EIRQ9, VCOUT3, TIM4_3_OVL, USART1_RTS, KEYOUT6, USBHS_ULPI_D4, EXMC_DATA14, QSPI_IO1 (FG1).
57 PD10 bidirectional GPIO PD10 with EIRQ10, CAN2_TST_SAMPLE, TIM4_3_OWL, USART3_CK, KEYOUT5, EXMC_DATA15, I2S2_EXCK, QSPI_IO2 (FG1).
58 PD11 bidirectional GPIO PD11 with EIRQ11, CAN2_TST_CLOCK, TIM4_3_CLK, USART3_CTS, KEYOUT4, EXMC_ADD16, I2S2_MCK, QSPI_IO3 (FG1).
59 PD12 bidirectional GPIO PD12 with EIRQ12, TIM4_1_ADSM, USART3_RTS, EXMC_ADD17 and TIMA_4/TIMA_11 alternate functions (FG3).
60 PD13 bidirectional GPIO PD13 with EIRQ13, TIM4_1_PCT, USART9_RTS, EXMC_ADD18 and TIMA_4/TIMA_11 alternate functions (FG3).
61 PD14 bidirectional GPIO PD14 with EIRQ14, ADTRG1, USART9_CTS, EXMC_DATA0, I2S4_EXCK (FG3).
62 PD15 bidirectional GPIO PD15 with EIRQ15, ADTRG2, USART9_CK, EXMC_DATA1, I2S4_MCK (FG3).
63 PC6 bidirectional GPIO PC6 with EIRQ6, CTCREF, TIM4_2_OUH, KEYOUT3, SDIO1_D6, DVP_DATA0, I2S1_MCK, QSPI_SCK, USART6_TX (FG3).
64 PC7 bidirectional GPIO PC7 with EIRQ7, TIM4_2_OVH, KEYOUT2, SDIO1_D7, DVP_DATA1, I2S2_MCK, QSPI_NSS, USART6_RX (FG3).
65 PC8 bidirectional GPIO PC8 with EIRQ8, TIM4_2_OWH, USART8_CK, KEYOUT1, SDIO1_D0, DVP_DATA2, I2S2_MCK, USART6_CK (FG2).
66 PC9 bidirectional GPIO PC9 with EIRQ9, MCO_2, TIM4_2_OWL, KEYOUT0, SDIO1_D1, USBFS_DRVVBUS, EXMC_CLE, DVP_DATA3, I2S3_EXCK (FG2).
67 PA8 bidirectional GPIO PA8 with EIRQ8/WKUP2_0, MCO_1, TIM4_1_OUH, USART4_CK, SDIO1_D1, USBFS_SOF, I2S3_MCK, USART1_CK (FG2).
68 PA9 bidirectional GPIO PA9 with EIRQ9/WKUP2_1, TIM4_1_OVH, SDIO1_D2, USBFS_VBUS, DVP_DATA0, I2S3_SDIN, USART1_TX (FG2).
69 PA10 bidirectional GPIO PA10 with EIRQ10/WKUP2_2, TIM4_1_OWH, SDIO1_CD, USBFS_ID, DVP_DATA1, USART1_RX (FG2).
70 PA11 bidirectional GPIO PA11 or USBFS_DM (USB full-speed PHY D-) with EIRQ11/WKUP2_3, TIM4_1_CLK, USART4_CTS, SDIO2_CD, USART1_CTS; not 5 V tolerant (FG2).
71 PA12 bidirectional GPIO PA12 or USBFS_DP (USB full-speed PHY D+) with EIRQ12/WKUP3_0, TIM4_3_OWL, USART4_RTS, SDIO2_WP, USART1_RTS; not 5 V tolerant (FG2).
72 PA13 bidirectional GPIO PA13 or JTMS_SWDIO (JTAG/SWD debug data) with EIRQ13, SDIO2_D3 and SPI2_NSS1 alternate functions (FG2).
73 VCAP_2 passive Core voltage regulator capacitor pin; connect 0.047 µF or 0.1 µF (ESR < 0.3 Ω) close to VSS.
74 VSS power_in Digital ground (0 V); decouple close to the paired VCC pin.
75 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple to VSS with nearby capacitors.
76 PA14 bidirectional GPIO PA14 or JTCK_SWCLK (JTAG/SWD debug clock) with EIRQ14/WKUP3_2, USART2_RTS, SDIO2_D2, I2S1_EXCK, SPI2_NSS2 (FG1).
77 PA15 bidirectional GPIO PA15 or JTDI (JTAG data input) with EIRQ15/WKUP3_3, USART2_CTS, SDIO2_D1, I2S1_MCK, SPI2_NSS3, SPI1_NSS0 (FG1).
78 PC10 bidirectional GPIO PC10 with EIRQ10, CAN1_TST_SAMPLE, TIM4_3_OUH, USART2_CK, SDIO1_D2, DVP_DATA8, I2S2_CK, SPI3_SCK, USART4_TX (FG3).
79 PC11 bidirectional GPIO PC11 with EIRQ11, CAN1_TST_CLOCK, TIM4_3_OVH, KEYOUT0, SDIO1_D3, DVP_DATA4, I2S2_SDIN, SPI3_MISO, USART4_RX (FG3).
80 PC12 bidirectional GPIO PC12 with EIRQ12, TIM4_3_OWH, USART3_CK, KEYOUT1, SDIO1_CK, DVP_DATA9, I2S2_SD, SPI3_MOSI, USART5_TX (FG3).
81 PD0 bidirectional GPIO PD0 with EIRQ0, VCOUT, TIM4_3_OUL, USART8_CTS, KEYOUT2, EXMC_DATA2 (FG3).
82 PD1 bidirectional GPIO PD1 with EIRQ1, TIM4_3_OVL, USART8_RTS, KEYOUT3, EXMC_DATA3 (FG3).
83 PD2 bidirectional GPIO PD2 with EIRQ2, VCOUT4, TIM4_3_OWL, USART7_CTS, KEYOUT4, SDIO1_CMD, DVP_DATA11, USART5_RX (FG3).
84 PD3 bidirectional GPIO PD3 with EIRQ3, VCOUT1, USART5_CTS, KEYOUT5, EXMC_CLK, DVP_DATA5, SPI2_SCK, USART2_CTS (FG3).
85 PD4 bidirectional GPIO PD4 with EIRQ4, VCOUT2, EMB_PORT4, USART5_RTS, KEYOUT6, EXMC_OE, DVP_DATA12, USART2_RTS (FG2).
86 PD5 bidirectional GPIO PD5 with EIRQ5, VCOUT3, USART7_RTS, KEYOUT7, EXMC_WE, SPI6_NSS1, USART2_TX (FG2).
87 PD6 bidirectional GPIO PD6 with EIRQ6, ADTRG1, TIM4_2_CLK, USART7_CK, EXMC_RB0, DVP_DATA10, I2S2_SD, SPI6_NSS2, SPI3_MOSI, USART2_RX (FG2).
88 PD7 bidirectional GPIO PD7 with EIRQ7, ADTRG2, EMB_PORT1, USART5_CK, EXMC_CE0, SPI6_NSS3, USART2_CK (FG2).
89 PB3 bidirectional GPIO PB3 or JTDO_TRACESWO (JTAG data output/trace SWO) with EIRQ3/WKUP0_3, FCMREF, TIM4_3_CLK, SDIO2_D0 (FG1).
90 PB4 bidirectional GPIO PB4 or NJTRST (JTAG reset) with EIRQ4/WKUP1_0, TIM4_3_OWL, SDIO1_D0, DVP_DATA13, I2S2_SDIN (FG1).
91 PB5 bidirectional GPIO PB5 with EIRQ5/WKUP1_1, ADTRG3, TIM4_3_OWH, SDIO1_D3, USBHS_ULPI_D7, ETH_PPS_OUT, EXMC_ALE, DVP_DATA10, I2S4_EXCK, SPI3_NSS3 (FG1).
92 PB6 bidirectional GPIO PB6 with EIRQ6/WKUP1_2, ADTRG2, TIM4_3_OVL, SDIO2_CK, ETH_MII_TXCLK, EXMC_CE1, DVP_DATA5, I2S4_MCK, SPI3_NSS2 (FG1).
93 PB7 bidirectional GPIO PB7 with EIRQ7/WKUP1_3, ADTRG1, TIM4_3_OVH, SDIO1_D0, ETH_MII_TXER, EXMC_ADV, DVP_VSYNC, I2S2_EXCK, SPI3_NSS1 (FG1).
94 PI13/MD bidirectional Mode input MD, which must be held low when NRST is released (4.7 kΩ pull-down to VSS recommended); also GPIO PI13 with USART3_TX.
95 PB8 bidirectional GPIO PB8 with EIRQ8, TIM4_3_OUL, USART1_CK, KEYOUT7, SDIO1_D4, USBFS_DRVVBUS, ETH_MII_TXD3, DVP_DATA6, I2S2_MCK, SPI2_NSS0 (FG1).
96 PB9 bidirectional GPIO PB9 with EIRQ9, TIM4_3_OUH, USART1_CTS, KEYOUT6, SDIO1_D5, ETH_MII_TXD2, DVP_DATA7, I2S2_SDIN, SPI2_NSS1/NSS0 (FG1).
97 PE0 bidirectional GPIO PE0 with EIRQ0, MCO_1, TIM4_3_PCT, USART1_RTS, ETH_MII_RMII_TXD1, EXMC_CE4, DVP_DATA2, SPI2_NSS2, USART8_RX (FG1).
98 PE1 bidirectional GPIO PE1 with EIRQ1, MCO_2, TIM4_3_CLK, ETH_MII_RMII_TXD0, EXMC_CE5, DVP_DATA3, SPI2_NSS3, USART8_TX (FG1).
99 VSS power_in Digital ground (0 V); decouple close to the paired VCC pin.
100 VCC power_in Digital supply, 1.8 V to 3.6 V; decouple to VSS with nearby capacitors.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
System supply voltage VCC 1.8 3.6 V 15
Operating temperature range -40 105 °C 15
Schmitt input low level VIL 0.2 xVCC 1.8≤VCC≤3.6 85
Schmitt input high level VIH 0.8 xVCC 1.8≤VCC≤3.6 85
Schmitt input hysteresis VHYS 0.2 V 1.8≤VCC≤3.6 85
CMOS input low level VIL 0.3 xVCC 1.8≤VCC≤3.6 85
CMOS input high level VIH 0.7 xVCC 1.8≤VCC≤3.6 85
I/O input leakage current ILKG 1 µA VSS≤VIN≤VCC 85
I/O input leakage current ILKG 10 µA VIN = 5.5V 85
Weak pull-up equivalent resistance RPU 30 kΩ VIN = VSS 85
Weak pull-down equivalent resistance (USB pins) RPD 500 kΩ PA11/PA12/PB14/PB15, VIN = VCC 85
I/O pin capacitance (USB pins) CIO 10 pF PA11/USBFS_DM, PA12/USBFS_DP, PB14/USBHS_DM, PB15/USBHS_DP 85
I/O pin capacitance (other pins) CIO 5 pF Input pins other than the USB pins 85
Low-drive output low level VOL 0.6 V IIO=±1.5mA, 1.8≤VCC<2.7 87
Low-drive output low level VOL 1.3 V IIO=±6mA, 2.7≤VCC≤3.6 87
Medium-drive output low level VOL 0.4 V IIO=±3mA, 1.8≤VCC<2.7 87
Medium-drive output low level VOL 1.3 V IIO=±12mA, 2.7≤VCC≤3.6 87
High-drive output low level VOL 0.4 V IIO=±6mA, 1.8≤VCC<2.7 87
High-drive output low level VOL 1.3 V IIO=±20mA, 2.7≤VCC≤3.6 87
HRPWM resolution t_hrpwmres 50 ps 90
USB FS operating voltage VCC 3 3.6 V 97
USB FS input low level VIL 0.8 V 97
USB FS input high level VIH 2 V 97
USB FS differential input sensitivity VDI 0.2 V 97
USB FS differential common mode voltage VCM 0.8 2.5 V 97
USB FS static output low level VOL 0.3 V RL=1.5kΩ to 3.6V 97
USB FS static output high level VOH 2.8 3.6 V RL=15kΩ to VSS 97
USB FS cross-over voltage VCRS 1.3 2 V CL=50pF 97
USB FS rise time tR 4 20 ns CL=50pF, 10%~90% of /VOH-VOL/ 97
USB FS fall time tF 4 20 ns CL=50pF, 10%~90% of /VOH-VOL/ 97
USB FS rise/fall time matching tRFMA 90 111 % CL=50pF 97
USB FS pull-up resistance RPU 0.9 1.2 1.575 kΩ VIN= VSS, idle state 97
USB FS pull-up resistance RPU 1.425 2.3 3.09 kΩ VIN= VSS, in device mode 97
USB pull-down resistance RPD 15 kΩ VIN= VCC, in host mode 97
USB driver output impedance ZDRV 28 36 44 Ω Driving high or low 97
USB LS rise time tR 75 300 ns CL=200pF~600pF, 10%~90% of /VOH-VOL/ 98
USB LS fall time tF 75 300 ns CL=200pF~600pF, 10%~90% of /VOH-VOL/ 98
USB LS rise/fall time matching tRFMA 80 125 % CL=200pF~600pF 98
USB LS cross-over voltage VCRS 1.3 2 V CL=200pF~600pF 98
ULPI control signal setup time tSC 3 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 99
ULPI control signal hold time tHC 2 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 99
ULPI data setup time tSD 3 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 99
ULPI data hold time tHD 2.2 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 99
ULPI data/control output delay tDC/tDD 4.5 7.5 10.6 ns 2.7V≤Vcc≤3.6V, CL=20pF, -40~105℃ 99
PGA analog supply voltage VAVCC 1.8 3.3 3.6 V 124
PGA input offset voltage VOS -8 8 mV 124
PGA gain error, Gain=2, external PGAVSS GE -1 1 % External port PGAVSS as negative input, Gain=2 124
PGA gain error, Gain=4.0, external PGAVSS GE -1.5 1.5 % External port PGAVSS as negative input, Gain=4.0 124
PGA gain error, Gain=32, external PGAVSS GE -7 7 % External port PGAVSS as negative input, Gain=32 124
PGA gain error, Gain=2, internal AVSS GE -2 2 % Internal analog ground AVSS as negative input, Gain=2 124
PGA gain error, Gain=32, internal AVSS GE -8 8 % Internal analog ground AVSS as negative input, Gain=32 124
VBAT low voltage detect threshold VBATLVD 1.7 1.8 1.9 V PWC_PWRC4.VBATREFSEL=0 125
VBAT low voltage detect threshold VBATLVD 2 2.1 2.2 V PWC_PWRC4.VBATREFSEL=1 125
EIRQ input filter width WF_EIRQ 0.4 0.9 us INTC_NOCCR.NOCSEL = 00b 125
EIRQ input filter width WF_EIRQ 3.1 5.9 us INTC_NOCCR.NOCSEL = 11b 125

CAD (KiCad official)

  • Symbol: HC32F4A0PGTB-LQFP100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: hc32f4a0pgtb-lqfp100-etched.step / hc32f4a0pgtb-lqfp100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f4a0pgtb-lqfp100.step / hc32f4a0pgtb-lqfp100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (139 pp, sha256 876919ca5e4e26d1, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF