component
HC32F460PETB-LQFP100
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HC32F460PETB-LQFP100
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
HC32F460PETB-LQFP100 from XHSC, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACECK trace clock output. |
| 2 | PE3 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED0 trace data output. |
| 3 | PE4 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED1 trace data output. |
| 4 | PE5 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED2 trace data output. |
| 5 | PE6 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED3 trace data output. |
| 6 | PH2 | bidirectional | GPIO port H pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate functions include FCMREF and SDIO2_D4. |
| 7 | PC13 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes RTC_OUT. |
| 8 | PC14/XTAL32_OUT | output | 32.768 kHz crystal oscillator output (XTAL32_OUT) that is also usable as GPIO PC14 when the oscillator is not used. |
| 9 | PC15/XTAL32_IN | input | 32.768 kHz crystal oscillator input (XTAL32_IN) that is also usable as GPIO PC15 when the oscillator is not used. |
| 10 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 11 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 12 | PH0/XTAL_IN | input | External main crystal oscillator input (XTAL_IN) for 4-25 MHz, also usable as GPIO PH0 with input voltage not exceeding 5 V. |
| 13 | PH1/XTAL_OUT | output | External main crystal oscillator output (XTAL_OUT), also usable as GPIO PH1 when the oscillator is not used. |
| 14 | NRST | input | Active-low reset pin with a minimum pulse width of 500 ns; connect a pull-up resistor to VCC if not used. |
| 15 | PC0/ADC12_IN10 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 16 | PC1/ADC12_IN11 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 17 | PC2/ADC1_IN12 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 18 | PC3/ADC1_IN13 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 19 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 20 | AVSS/VREFL | power_in | Analog ground pin (AVSS), equal to VSS; the figure labels this pin AVSS/VREFL, while the table lists only AVSS for this LQFP100 pin. |
| 21 | VREFH | power_in | ADC1/ADC2 analog reference voltage input that must not exceed AVCC; tie to AVCC when the ADC is not used. |
| 22 | AVCC | power_in | Analog supply pin at the same voltage as VCC (1.8 V to 3.6 V); tie to VCC when analog modules are not used. |
| 23 | PA0/ADC1_IN0 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OUH. |
| 24 | PA1/ADC1_IN1 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OUL. |
| 25 | PA2/ADC1_IN2 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OVH. |
| 26 | PA3/ADC1_IN3 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes PGAVSS analog ground input. |
| 27 | AVSS | power_in | Analog ground pin, equal to VSS. |
| 28 | AVCC | power_in | Analog supply pin at the same voltage as VCC (1.8 V to 3.6 V); tie to VCC when analog modules are not used. |
| 29 | PA4/ADC12_IN4 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART2_CK. |
| 30 | PA5/ADC12_IN5 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes KEYOUT1 and I2S1_MCK. |
| 31 | PA6/ADC12_IN6 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO1_CMD. |
| 32 | PA7/ADC12_IN7 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO2_WP. |
| 33 | PC4/ADC1_IN14 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART1_CK. |
| 34 | PC5/ADC1_IN15 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO2_CMD. |
| 35 | PB0/ADC12_IN8 | bidirectional | GPIO port B pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART4_CK. |
| 36 | PB1/ADC12_IN9 | bidirectional | GPIO port B pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes QSPI_QSSN. |
| 37 | PB2/PVD2EXINP | bidirectional | GPIO port B pin; also the external comparison voltage input for PVD2 (PVD2EXINP), and digital input must not exceed 5 V. |
| 38 | PE7 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG1. |
| 39 | PE8 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OUL. |
| 40 | PE9 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OUH. |
| 41 | PE10 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OVL. |
| 42 | PE11 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OVH. |
| 43 | PE12 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS1. |
| 44 | PE13 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS2. |
| 45 | PE14 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS3. |
| 46 | PE15 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART4_CK. |
| 47 | PB10 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG2. |
| 48 | VCAP_1 | passive | Core voltage stabilization pin; connect an external capacitor (0.047 µF, 0.1 µF or 0.22 µF, ESR < 0.3 Ω) close to VSS as specified in Table 3-1. |
| 49 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 50 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 51 | PB12 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT1. |
| 52 | PB13 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT2. |
| 53 | PB14 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT3. |
| 54 | PB15 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes RTC_OUT. |
| 55 | PD8 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT7. |
| 56 | PD9 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT6. |
| 57 | PD10 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT5. |
| 58 | PD11 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT4. |
| 59 | PD12 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM1. |
| 60 | PD13 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM2. |
| 61 | PD14 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM3. |
| 62 | PD15 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM4. |
| 63 | PC6 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes QSPI_QSCK. |
| 64 | PC7 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes QSPI_QSSN. |
| 65 | PC8 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART3_CK. |
| 66 | PC9 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_2. |
| 67 | PA8 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_1 and USBFS_SOF. |
| 68 | PA9 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_VBUS. |
| 69 | PA10 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_ID. |
| 70 | PA11 | bidirectional | GPIO port A pin with pull-up and push-pull/open-drain; not 5 V tolerant, input voltage must not exceed VCC+0.3 V; shared with USBFS_DM (USB full-speed D-). |
| 71 | PA12 | bidirectional | GPIO port A pin with pull-up and push-pull/open-drain; not 5 V tolerant, input voltage must not exceed VCC+0.3 V; shared with USBFS_DP (USB full-speed D+). |
| 72 | PA13/JTMS_SWDIO | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; serves as JTMS/SWDIO debug data pin. |
| 73 | VCAP_2 | passive | Core voltage stabilization pin; connect a capacitor close to VSS, with total VCAP_1/VCAP_2 capacitance matching PWC_PWRC3.PDTS as specified in Table 3-1. |
| 74 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 75 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 76 | PA14/JTCK_SWCLK | input | GPIO port A pin with pull-up and input voltage not exceeding 5 V; serves as JTCK/SWCLK debug clock pin. |
| 77 | PA15/JTDI | input | GPIO port A pin with pull-up and input voltage not exceeding 5 V; serves as JTDI debug data input pin. |
| 78 | PC10 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_D2. |
| 79 | PC11 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_D3. |
| 80 | PC12 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_CK. |
| 81 | PD0 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT123. |
| 82 | PD1 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_3_TRIG. |
| 83 | PD2 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_CMD. |
| 84 | PD3 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT1. |
| 85 | PD4 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT2. |
| 86 | PD5 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT3. |
| 87 | PD6 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART2_CK. |
| 88 | PD7 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART2_CK. |
| 89 | PB3/JTDO_TRACESWO | output | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; serves as JTDO/TRACESWO debug output pin. |
| 90 | PB4/NJTRST | input | GPIO port B pin with pull-up and input voltage not exceeding 5 V; serves as NJTRST JTAG reset input pin. |
| 91 | PB5 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes I2S4_EXCK. |
| 92 | PB6 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG2. |
| 93 | PB7 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG1. |
| 94 | PB11/MD | input | Mode input pin, fixed as input and input-only on this port; must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC. |
| 95 | PB8 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_DRVVBUS. |
| 96 | PB9 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI2_SS1. |
| 97 | PE0 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_1. |
| 98 | PE1 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_2. |
| 99 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 100 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC | VCC | 1.8 | 3.6 | V | 12 | ||
| Operating ambient temperature (B suffix, industrial) | -40 | 105 | °C | B suffix (-40-105℃) | 11 | ||
| PLL PFD input clock fPLL_IN | fPLL_IN | 1 | 25 | MHz | 81 | ||
| PLL multiplier output clock fPLL_OUT | fPLL_OUT | 15 | 240 | MHz | 81 | ||
| PLL VCO output fVCO_OUT | fVCO_OUT | 240 | 480 | MHz | 81 | ||
| PLL lock time tLOCK | tLOCK | 80 | 120 | µs | 81 | ||
| Input clock cycles, UART | tcyc | 4 | tPCLK1 | UART | 73 | ||
| Input clock cycles, CSI | tcyc | 6 | tPCLK1 | CSI | 73 | ||
| Input clock width tCKw | tCKw | 0.4 | 0.6 | tScyc | 73 | ||
| Input clock rise time tCKr | tCKr | 5 | ns | 73 | |||
| Input clock fall time tCKf | tCKf | 5 | ns | 73 | |||
| Transmit delay tTD | tTD | 28 | ns | CSI | 73 | ||
| Receive data setup time tRDS | tRDS | 15 | ns | CSI | 73 | ||
| Receive data hold time tRDH | tRDH | 5 | ns | CSI | 73 | ||
| SPI SCK clock cycle, master | tspcyc | 2 | 4096 | tpcyc | pclk ≤60MHz | 77 | |
| SPI SCK clock cycle, slave | tspcyc | 6 | 4096 | tpcyc | 77 | ||
| SPI data input setup time, master | tsu | 4 | ns | 77 | |||
| SPI data input setup time, slave | tsu | 5 | ns | C=30pF | 77 | ||
| SPI data input hold time, slave | th | 20 | ns | 77 | |||
| SPI data output delay, master | tod | 8 | ns | 77 | |||
| SPI data output delay, slave | tod | 20 | ns | 77 | |||
| SPI data output hold time, master | toh | 0 | ns | 77 | |||
| SPI data output hold time, slave | toh | 0 | ns | 77 | |||
| SPI MOSI/MISO rise and fall time, master | tdr, tdf | 5 | ns | 77 | |||
| SPI MOSI/MISO rise and fall time, slave | tdr, tdf | 1 | us | 77 | |||
| SS rise and fall time, master | tssr, tssf | 5 | ns | 77 | |||
| SS rise and fall time, slave | tssr, tssf | 1 | us | 77 | |||
| VCC operating voltage (USB FS) | VCC | 3 | 3.6 | V | 79 | ||
| USB FS input low level | VIL | 0.8 | V | 79 | |||
| USB FS input high level | VIH | 2 | V | 79 | |||
| USB FS differential input sensitivity | VDI | 0.2 | V | 79 | |||
| USB FS differential common-mode voltage | VCM | 0.8 | 2.5 | V | 79 | ||
| USB FS static output low level | VOL | 0.3 | V | RL=1.5kΩ to 3.6V | 79 | ||
| USB FS static output high level | VOH | 2.8 | 3.6 | V | RL=15kΩ to VSS | 79 | |
| USB FS cross-over voltage | VCRS | 1.3 | 2 | V | CL=50pF | 79 | |
| USB FS rise time tR | tR | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 | |
| USB FS fall time tF | tF | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 | |
| USB FS rise/fall time ratio tRFMA | tRFMA | 90 | 111.1 | % | CL=50pF | 79 | |
| USB FS pull-up resistance, idle state | RPU | 0.9 | 1.2 | 1.575 | kΩ | VIN=VSS, idle state | 79 |
| USB FS pull-up resistance, device mode | RPU | 1.425 | 2.3 | 3.09 | kΩ | VIN=VSS, in device mode | 79 |
| I2C SCL frequency fSCL | fSCL | 0 | 100 | KHz | Standard mode (SM) | 76 | |
| I2C SCL frequency fSCL | fSCL | 0 | 400 | KHz | Fast mode (FM) | 76 | |
| I2C hold time START/repeated START tHD;STA | tHD;STA | 4 | us | Standard mode (SM) | 76 | ||
| I2C hold time START/repeated START tHD;STA | tHD;STA | 0.6 | us | Fast mode (FM) | 76 | ||
| I2C SCL low period tLOW | tLOW | 4.7 | us | Standard mode (SM) | 76 | ||
| I2C SCL low period tLOW | tLOW | 1.3 | us | Fast mode (FM) | 76 | ||
| I2C SCL high period tHIGH | tHIGH | 4 | us | Standard mode (SM) | 76 | ||
| I2C SCL high period tHIGH | tHIGH | 0.6 | us | Fast mode (FM) | 76 | ||
| I2C repeated START setup tSU;STA | tSU;STA | 4.7 | us | Standard mode (SM) | 76 | ||
| I2C repeated START setup tSU;STA | tSU;STA | 0.6 | us | Fast mode (FM) | 76 | ||
| I2C SCL/SDA rise time tR | tR | 1000 | ns | Standard mode (SM) | 76 | ||
| I2C SCL/SDA rise time tR | tR | 6.5 | 300 | ns | Fast mode (FM) | 76 | |
| I2C SCL/SDA fall time tF | tF | 300 | ns | Standard mode (SM) | 76 | ||
| I2C SCL/SDA fall time tF | tF | 6.5 | 300 | ns | Fast mode (FM) | 76 | |
| I2C STOP setup tSU;STO | tSU;STO | 4 | us | Standard mode (SM) | 76 | ||
| I2C STOP setup tSU;STO | tSU;STO | 0.6 | us | Fast mode (FM) | 76 | ||
| I2C bus free time tBUF | tBUF | 4.7 | us | Standard mode (SM) | 76 | ||
| I2C bus free time tBUF | tBUF | 1.3 | us | Fast mode (FM) | 76 | ||
| I2C load capacitance Cb | Cb | 400 | pF | Standard mode (SM) | 76 |
CAD (KiCad official)
- Symbol:
HC32F460PETB-LQFP100 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
hc32f460petb-lqfp100-etched.step/hc32f460petb-lqfp100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f460petb-lqfp100.step/hc32f460petb-lqfp100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (116 pp, sha256
df339d0329616ae4, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HC32F460PETB-LQFP100
**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
HC32F460PETB-LQFP100 from XHSC, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACECK trace clock output. |
| 2 | PE3 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED0 trace data output. |
| 3 | PE4 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED1 trace data output. |
| 4 | PE5 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED2 trace data output. |
| 5 | PE6 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TRACED3 trace data output. |
| 6 | PH2 | bidirectional | GPIO port H pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate functions include FCMREF and SDIO2_D4. |
| 7 | PC13 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes RTC_OUT. |
| 8 | PC14/XTAL32_OUT | output | 32.768 kHz crystal oscillator output (XTAL32_OUT) that is also usable as GPIO PC14 when the oscillator is not used. |
| 9 | PC15/XTAL32_IN | input | 32.768 kHz crystal oscillator input (XTAL32_IN) that is also usable as GPIO PC15 when the oscillator is not used. |
| 10 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 11 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 12 | PH0/XTAL_IN | input | External main crystal oscillator input (XTAL_IN) for 4-25 MHz, also usable as GPIO PH0 with input voltage not exceeding 5 V. |
| 13 | PH1/XTAL_OUT | output | External main crystal oscillator output (XTAL_OUT), also usable as GPIO PH1 when the oscillator is not used. |
| 14 | NRST | input | Active-low reset pin with a minimum pulse width of 500 ns; connect a pull-up resistor to VCC if not used. |
| 15 | PC0/ADC12_IN10 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 16 | PC1/ADC12_IN11 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 17 | PC2/ADC1_IN12 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 18 | PC3/ADC1_IN13 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V. |
| 19 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 20 | AVSS/VREFL | power_in | Analog ground pin (AVSS), equal to VSS; the figure labels this pin AVSS/VREFL, while the table lists only AVSS for this LQFP100 pin. |
| 21 | VREFH | power_in | ADC1/ADC2 analog reference voltage input that must not exceed AVCC; tie to AVCC when the ADC is not used. |
| 22 | AVCC | power_in | Analog supply pin at the same voltage as VCC (1.8 V to 3.6 V); tie to VCC when analog modules are not used. |
| 23 | PA0/ADC1_IN0 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OUH. |
| 24 | PA1/ADC1_IN1 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OUL. |
| 25 | PA2/ADC1_IN2 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes TIM4_2_OVH. |
| 26 | PA3/ADC1_IN3 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes PGAVSS analog ground input. |
| 27 | AVSS | power_in | Analog ground pin, equal to VSS. |
| 28 | AVCC | power_in | Analog supply pin at the same voltage as VCC (1.8 V to 3.6 V); tie to VCC when analog modules are not used. |
| 29 | PA4/ADC12_IN4 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART2_CK. |
| 30 | PA5/ADC12_IN5 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes KEYOUT1 and I2S1_MCK. |
| 31 | PA6/ADC12_IN6 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO1_CMD. |
| 32 | PA7/ADC12_IN7 | bidirectional | GPIO port A pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO2_WP. |
| 33 | PC4/ADC1_IN14 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART1_CK. |
| 34 | PC5/ADC1_IN15 | bidirectional | GPIO port C pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes SDIO2_CMD. |
| 35 | PB0/ADC12_IN8 | bidirectional | GPIO port B pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes USART4_CK. |
| 36 | PB1/ADC12_IN9 | bidirectional | GPIO port B pin; analog input must not exceed VREFH/AVCC, and digital input must not exceed 5 V; alternate function includes QSPI_QSSN. |
| 37 | PB2/PVD2EXINP | bidirectional | GPIO port B pin; also the external comparison voltage input for PVD2 (PVD2EXINP), and digital input must not exceed 5 V. |
| 38 | PE7 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG1. |
| 39 | PE8 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OUL. |
| 40 | PE9 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OUH. |
| 41 | PE10 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OVL. |
| 42 | PE11 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIM4_1_OVH. |
| 43 | PE12 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS1. |
| 44 | PE13 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS2. |
| 45 | PE14 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI1_SS3. |
| 46 | PE15 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART4_CK. |
| 47 | PB10 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG2. |
| 48 | VCAP_1 | passive | Core voltage stabilization pin; connect an external capacitor (0.047 µF, 0.1 µF or 0.22 µF, ESR < 0.3 Ω) close to VSS as specified in Table 3-1. |
| 49 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 50 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 51 | PB12 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT1. |
| 52 | PB13 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT2. |
| 53 | PB14 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT3. |
| 54 | PB15 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes RTC_OUT. |
| 55 | PD8 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT7. |
| 56 | PD9 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT6. |
| 57 | PD10 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT5. |
| 58 | PD11 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes KEYOUT4. |
| 59 | PD12 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM1. |
| 60 | PD13 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM2. |
| 61 | PD14 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM3. |
| 62 | PD15 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_4_PWM4. |
| 63 | PC6 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes QSPI_QSCK. |
| 64 | PC7 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes QSPI_QSSN. |
| 65 | PC8 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART3_CK. |
| 66 | PC9 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_2. |
| 67 | PA8 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_1 and USBFS_SOF. |
| 68 | PA9 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_VBUS. |
| 69 | PA10 | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_ID. |
| 70 | PA11 | bidirectional | GPIO port A pin with pull-up and push-pull/open-drain; not 5 V tolerant, input voltage must not exceed VCC+0.3 V; shared with USBFS_DM (USB full-speed D-). |
| 71 | PA12 | bidirectional | GPIO port A pin with pull-up and push-pull/open-drain; not 5 V tolerant, input voltage must not exceed VCC+0.3 V; shared with USBFS_DP (USB full-speed D+). |
| 72 | PA13/JTMS_SWDIO | bidirectional | GPIO port A pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; serves as JTMS/SWDIO debug data pin. |
| 73 | VCAP_2 | passive | Core voltage stabilization pin; connect a capacitor close to VSS, with total VCAP_1/VCAP_2 capacitance matching PWC_PWRC3.PDTS as specified in Table 3-1. |
| 74 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 75 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
| 76 | PA14/JTCK_SWCLK | input | GPIO port A pin with pull-up and input voltage not exceeding 5 V; serves as JTCK/SWCLK debug clock pin. |
| 77 | PA15/JTDI | input | GPIO port A pin with pull-up and input voltage not exceeding 5 V; serves as JTDI debug data input pin. |
| 78 | PC10 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_D2. |
| 79 | PC11 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_D3. |
| 80 | PC12 | bidirectional | GPIO port C pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_CK. |
| 81 | PD0 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT123. |
| 82 | PD1 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes TIMA_3_TRIG. |
| 83 | PD2 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SDIO1_CMD. |
| 84 | PD3 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT1. |
| 85 | PD4 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT2. |
| 86 | PD5 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes VCOUT3. |
| 87 | PD6 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART2_CK. |
| 88 | PD7 | bidirectional | GPIO port D pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USART2_CK. |
| 89 | PB3/JTDO_TRACESWO | output | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; serves as JTDO/TRACESWO debug output pin. |
| 90 | PB4/NJTRST | input | GPIO port B pin with pull-up and input voltage not exceeding 5 V; serves as NJTRST JTAG reset input pin. |
| 91 | PB5 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes I2S4_EXCK. |
| 92 | PB6 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG2. |
| 93 | PB7 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes ADTRG1. |
| 94 | PB11/MD | input | Mode input pin, fixed as input and input-only on this port; must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC. |
| 95 | PB8 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes USBFS_DRVVBUS. |
| 96 | PB9 | bidirectional | GPIO port B pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes SPI2_SS1. |
| 97 | PE0 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_1. |
| 98 | PE1 | bidirectional | GPIO port E pin with pull-up, push-pull/open-drain and low/medium/high drive; input voltage must not exceed 5 V; alternate function includes MCO_2. |
| 99 | VSS | power_in | Ground pin, 0 V; decouple with the VCC supply pins as shown in the power scheme. |
| 100 | VCC | power_in | Digital supply pin, 1.8 V to 3.6 V; place decoupling capacitors close to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC | VCC | 1.8 | | 3.6 | V | | 12 |
| Operating ambient temperature (B suffix, industrial) | | -40 | | 105 | °C | B suffix (-40-105℃) | 11 |
| PLL PFD input clock fPLL_IN | fPLL_IN | 1 | | 25 | MHz | | 81 |
| PLL multiplier output clock fPLL_OUT | fPLL_OUT | 15 | | 240 | MHz | | 81 |
| PLL VCO output fVCO_OUT | fVCO_OUT | 240 | | 480 | MHz | | 81 |
| PLL lock time tLOCK | tLOCK | | 80 | 120 | µs | | 81 |
| Input clock cycles, UART | tcyc | 4 | | | tPCLK1 | UART | 73 |
| Input clock cycles, CSI | tcyc | 6 | | | tPCLK1 | CSI | 73 |
| Input clock width tCKw | tCKw | 0.4 | | 0.6 | tScyc | | 73 |
| Input clock rise time tCKr | tCKr | | | 5 | ns | | 73 |
| Input clock fall time tCKf | tCKf | | | 5 | ns | | 73 |
| Transmit delay tTD | tTD | | | 28 | ns | CSI | 73 |
| Receive data setup time tRDS | tRDS | 15 | | | ns | CSI | 73 |
| Receive data hold time tRDH | tRDH | 5 | | | ns | CSI | 73 |
| SPI SCK clock cycle, master | tspcyc | 2 | | 4096 | tpcyc | pclk ≤60MHz | 77 |
| SPI SCK clock cycle, slave | tspcyc | 6 | | 4096 | tpcyc | | 77 |
| SPI data input setup time, master | tsu | 4 | | | ns | | 77 |
| SPI data input setup time, slave | tsu | 5 | | | ns | C=30pF | 77 |
| SPI data input hold time, slave | th | 20 | | | ns | | 77 |
| SPI data output delay, master | tod | | | 8 | ns | | 77 |
| SPI data output delay, slave | tod | | | 20 | ns | | 77 |
| SPI data output hold time, master | toh | 0 | | | ns | | 77 |
| SPI data output hold time, slave | toh | 0 | | | ns | | 77 |
| SPI MOSI/MISO rise and fall time, master | tdr, tdf | | | 5 | ns | | 77 |
| SPI MOSI/MISO rise and fall time, slave | tdr, tdf | | | 1 | us | | 77 |
| SS rise and fall time, master | tssr, tssf | | | 5 | ns | | 77 |
| SS rise and fall time, slave | tssr, tssf | | | 1 | us | | 77 |
| VCC operating voltage (USB FS) | VCC | 3 | | 3.6 | V | | 79 |
| USB FS input low level | VIL | | | 0.8 | V | | 79 |
| USB FS input high level | VIH | 2 | | | V | | 79 |
| USB FS differential input sensitivity | VDI | 0.2 | | | V | | 79 |
| USB FS differential common-mode voltage | VCM | 0.8 | | 2.5 | V | | 79 |
| USB FS static output low level | VOL | | | 0.3 | V | RL=1.5kΩ to 3.6V | 79 |
| USB FS static output high level | VOH | 2.8 | | 3.6 | V | RL=15kΩ to VSS | 79 |
| USB FS cross-over voltage | VCRS | 1.3 | | 2 | V | CL=50pF | 79 |
| USB FS rise time tR | tR | 4 | | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 |
| USB FS fall time tF | tF | 4 | | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 |
| USB FS rise/fall time ratio tRFMA | tRFMA | 90 | | 111.1 | % | CL=50pF | 79 |
| USB FS pull-up resistance, idle state | RPU | 0.9 | 1.2 | 1.575 | kΩ | VIN=VSS, idle state | 79 |
| USB FS pull-up resistance, device mode | RPU | 1.425 | 2.3 | 3.09 | kΩ | VIN=VSS, in device mode | 79 |
| I2C SCL frequency fSCL | fSCL | 0 | | 100 | KHz | Standard mode (SM) | 76 |
| I2C SCL frequency fSCL | fSCL | 0 | | 400 | KHz | Fast mode (FM) | 76 |
| I2C hold time START/repeated START tHD;STA | tHD;STA | 4 | | | us | Standard mode (SM) | 76 |
| I2C hold time START/repeated START tHD;STA | tHD;STA | 0.6 | | | us | Fast mode (FM) | 76 |
| I2C SCL low period tLOW | tLOW | 4.7 | | | us | Standard mode (SM) | 76 |
| I2C SCL low period tLOW | tLOW | 1.3 | | | us | Fast mode (FM) | 76 |
| I2C SCL high period tHIGH | tHIGH | 4 | | | us | Standard mode (SM) | 76 |
| I2C SCL high period tHIGH | tHIGH | 0.6 | | | us | Fast mode (FM) | 76 |
| I2C repeated START setup tSU;STA | tSU;STA | 4.7 | | | us | Standard mode (SM) | 76 |
| I2C repeated START setup tSU;STA | tSU;STA | 0.6 | | | us | Fast mode (FM) | 76 |
| I2C SCL/SDA rise time tR | tR | | | 1000 | ns | Standard mode (SM) | 76 |
| I2C SCL/SDA rise time tR | tR | 6.5 | | 300 | ns | Fast mode (FM) | 76 |
| I2C SCL/SDA fall time tF | tF | | | 300 | ns | Standard mode (SM) | 76 |
| I2C SCL/SDA fall time tF | tF | 6.5 | | 300 | ns | Fast mode (FM) | 76 |
| I2C STOP setup tSU;STO | tSU;STO | 4 | | | us | Standard mode (SM) | 76 |
| I2C STOP setup tSU;STO | tSU;STO | 0.6 | | | us | Fast mode (FM) | 76 |
| I2C bus free time tBUF | tBUF | 4.7 | | | us | Standard mode (SM) | 76 |
| I2C bus free time tBUF | tBUF | 1.3 | | | us | Fast mode (FM) | 76 |
| I2C load capacitance Cb | Cb | | | 400 | pF | Standard mode (SM) | 76 |
## CAD (KiCad official)
- Symbol: `HC32F460PETB-LQFP100`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `hc32f460petb-lqfp100-etched.step` / `hc32f460petb-lqfp100-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f460petb-lqfp100.step` / `hc32f460petb-lqfp100.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893367132696576) (116 pp, sha256 `df339d0329616ae4`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hc32f460petb-lqfp100-datasheet.pdf)