component
HC32F460JEUA-QFN48TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), QFN-48-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HC32F460JEUA-QFN48TR
XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(5x5)
HC32F460JEUA-QFN48TR from XHSC, in a QFN-48-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | Port H general-purpose I/O (5 V tolerant) with alternate functions including EIRQ2, FCMREF, SDIO2_D4 and I2S3_EXCK; input voltage must not exceed 5 V. |
| 2 | PC13 | bidirectional | Port C general-purpose I/O (5 V tolerant) with alternate functions including RTC_OUT, SDIO2_CK and I2S3_MCK; input voltage must not exceed 5 V. |
| 3 | PC14/XTAL32_OUT | bidirectional | Port C general-purpose I/O (5 V tolerant) that doubles as the output of the external 32.768 kHz oscillator (XTAL32_OUT). |
| 4 | PC15/XTAL32_IN | bidirectional | Port C general-purpose I/O (5 V tolerant) that doubles as the input of the external 32.768 kHz oscillator (XTAL32_IN); the crystal and its load capacitors must sit close to the pins. |
| 5 | PH0/XTAL_IN | input | External high-speed oscillator input for a 4-25 MHz crystal or resonator, or an external clock of 1-25 MHz. |
| 6 | PH1/XTAL_OUT | output | External high-speed oscillator output for a 4-25 MHz crystal or resonator. |
| 7 | NRST | input | Active-low reset input with a minimum low pulse width of 500 ns; if unused, connect a pull-up resistor to VCC. |
| 8 | AVSS/VREFL | power_in | Analog ground and ADC low reference; tie to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply (1.8-3.6 V, same voltage as VCC) and ADC high reference VREFH, which must not exceed AVCC; tie to AVCC if the ADC is not used. |
| 10 | PA0/ADC1_IN0 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 0; analog voltage must not exceed VREFH/AVCC. |
| 11 | PA1/ADC1_IN1 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 1; analog voltage must not exceed VREFH/AVCC. |
| 12 | PA2/ADC1_IN2 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 2; analog voltage must not exceed VREFH/AVCC. |
| 13 | PA3/ADC1_IN3 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 3 and PGA ground reference (PGAVSS); analog voltage must not exceed VREFH/AVCC. |
| 14 | PA4/ADC12_IN4 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 4; analog voltage must not exceed VREFH/AVCC. |
| 15 | PA5/ADC12_IN5 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 5; analog voltage must not exceed VREFH/AVCC. |
| 16 | PA6/ADC12_IN6 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 6; analog voltage must not exceed VREFH/AVCC. |
| 17 | PA7/ADC12_IN7 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 7; analog voltage must not exceed VREFH/AVCC. |
| 18 | PB0/ADC12_IN8 | bidirectional | Port B general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 8; analog voltage must not exceed VREFH/AVCC. |
| 19 | PB1/ADC12_IN9 | bidirectional | Port B general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 9; analog voltage must not exceed VREFH/AVCC. |
| 20 | PB2/PVD2EXINP | bidirectional | Port B general-purpose I/O (5 V tolerant) that doubles as the external comparison input of PVD2 (PVD2EXINP). |
| 21 | PB10 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including EIRQ10, ADTRG2 and I2S3_EXCK; input voltage must not exceed 5 V. |
| 22 | VCAP_1 | passive | Core voltage regulator stabilisation pin; connect an external capacitor (0.047, 0.1 or 0.22 µF, ESR < 0.3 Ω) between this pin and a nearby VSS pin. |
| 23 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 24 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 25 | PB12 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT1, QSPI_QSIO1 and SDIO2_D1; input voltage must not exceed 5 V. |
| 26 | PB13 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT2, QSPI_QSIO0 and SDIO2_D0; input voltage must not exceed 5 V. |
| 27 | PB14 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT3, QSPI_QSCK and SDIO1_D6; input voltage must not exceed 5 V. |
| 28 | PB15 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including RTC_OUT, USART3_CK and SDIO1_CK; input voltage must not exceed 5 V. |
| 29 | PA8 | bidirectional | Port A general-purpose I/O (5 V tolerant) with alternate functions including MCO_1, USART1_CK, SDIO1_D1 and USBFS_SOF; input voltage must not exceed 5 V. |
| 30 | PA9/USBFS_VBUS | bidirectional | Port A general-purpose I/O (5 V tolerant) that doubles as the USB FS VBUS detection input (USBFS_VBUS); input voltage must not exceed 5 V. |
| 31 | PA10/USBFS_ID | bidirectional | Port A general-purpose I/O (5 V tolerant) that doubles as the USB FS ID input (USBFS_ID); input voltage must not exceed 5 V. |
| 32 | PA11/USBFS_DM | bidirectional | USB FS D- line of the on-chip full-speed PHY; not 5 V tolerant, input voltage must not exceed VCC+0.3 V. |
| 33 | PA12/USBFS_DP | bidirectional | USB FS D+ line of the on-chip full-speed PHY; not 5 V tolerant, input voltage must not exceed VCC+0.3 V. |
| 34 | PA13/JTMS_SWDIO | bidirectional | Port A general-purpose I/O (5 V tolerant) that serves as the JTAG TMS / SWD data pin (JTMS_SWDIO) for debug. |
| 35 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 36 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 37 | PA14/JTCK_SWCLK | input | Port A I/O (5 V tolerant) that serves as the JTAG clock / SWD clock input (JTCK_SWCLK) for debug. |
| 38 | PA15/JTDI | input | Port A I/O (5 V tolerant) that serves as the JTAG data input (JTDI) for debug. |
| 39 | PB3/JTDO_TRACESWO | output | Port B I/O that serves as the JTAG data output / trace SWO (JTDO_TRACESWO) for debug. |
| 40 | PB4/NJTRST | input | Port B I/O that serves as the active-low JTAG reset input (NJTRST) for debug. |
| 41 | PB5 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OWH, SDIO1_D3 and I2S4_EXCK; input voltage must not exceed 5 V. |
| 42 | PB6 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including ADTRG2, SDIO2_CK and I2S4_MCK; input voltage must not exceed 5 V. |
| 43 | PB7 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including ADTRG1, SDIO1_D0 and TIMA_4_PWM2; input voltage must not exceed 5 V. |
| 44 | PB11/MD | input | Mode input, fixed as input and input-only (5 V tolerant); must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC. |
| 45 | PB8 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OUL, KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS; input voltage must not exceed 5 V. |
| 46 | PB9 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OUH, SPI2_SS1, KEYOUT6 and SDIO1_D5; input voltage must not exceed 5 V. |
| 47 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 48 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
HC32F460JEUA-QFN48TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm - 3D model: QFN-48-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
hc32f460jeua-qfn48tr-etched.step/hc32f460jeua-qfn48tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f460jeua-qfn48tr.step/hc32f460jeua-qfn48tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (116 pp, sha256
df339d0329616ae4, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HC32F460JEUA-QFN48TR
**XHSC** · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(5x5)
HC32F460JEUA-QFN48TR from XHSC, in a QFN-48-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | Port H general-purpose I/O (5 V tolerant) with alternate functions including EIRQ2, FCMREF, SDIO2_D4 and I2S3_EXCK; input voltage must not exceed 5 V. |
| 2 | PC13 | bidirectional | Port C general-purpose I/O (5 V tolerant) with alternate functions including RTC_OUT, SDIO2_CK and I2S3_MCK; input voltage must not exceed 5 V. |
| 3 | PC14/XTAL32_OUT | bidirectional | Port C general-purpose I/O (5 V tolerant) that doubles as the output of the external 32.768 kHz oscillator (XTAL32_OUT). |
| 4 | PC15/XTAL32_IN | bidirectional | Port C general-purpose I/O (5 V tolerant) that doubles as the input of the external 32.768 kHz oscillator (XTAL32_IN); the crystal and its load capacitors must sit close to the pins. |
| 5 | PH0/XTAL_IN | input | External high-speed oscillator input for a 4-25 MHz crystal or resonator, or an external clock of 1-25 MHz. |
| 6 | PH1/XTAL_OUT | output | External high-speed oscillator output for a 4-25 MHz crystal or resonator. |
| 7 | NRST | input | Active-low reset input with a minimum low pulse width of 500 ns; if unused, connect a pull-up resistor to VCC. |
| 8 | AVSS/VREFL | power_in | Analog ground and ADC low reference; tie to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply (1.8-3.6 V, same voltage as VCC) and ADC high reference VREFH, which must not exceed AVCC; tie to AVCC if the ADC is not used. |
| 10 | PA0/ADC1_IN0 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 0; analog voltage must not exceed VREFH/AVCC. |
| 11 | PA1/ADC1_IN1 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 1; analog voltage must not exceed VREFH/AVCC. |
| 12 | PA2/ADC1_IN2 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 2; analog voltage must not exceed VREFH/AVCC. |
| 13 | PA3/ADC1_IN3 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as ADC1 analog input 3 and PGA ground reference (PGAVSS); analog voltage must not exceed VREFH/AVCC. |
| 14 | PA4/ADC12_IN4 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 4; analog voltage must not exceed VREFH/AVCC. |
| 15 | PA5/ADC12_IN5 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 5; analog voltage must not exceed VREFH/AVCC. |
| 16 | PA6/ADC12_IN6 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 6; analog voltage must not exceed VREFH/AVCC. |
| 17 | PA7/ADC12_IN7 | bidirectional | Port A general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 7; analog voltage must not exceed VREFH/AVCC. |
| 18 | PB0/ADC12_IN8 | bidirectional | Port B general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 8; analog voltage must not exceed VREFH/AVCC. |
| 19 | PB1/ADC12_IN9 | bidirectional | Port B general-purpose I/O (5 V tolerant) also used as shared ADC1/ADC2 analog input 9; analog voltage must not exceed VREFH/AVCC. |
| 20 | PB2/PVD2EXINP | bidirectional | Port B general-purpose I/O (5 V tolerant) that doubles as the external comparison input of PVD2 (PVD2EXINP). |
| 21 | PB10 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including EIRQ10, ADTRG2 and I2S3_EXCK; input voltage must not exceed 5 V. |
| 22 | VCAP_1 | passive | Core voltage regulator stabilisation pin; connect an external capacitor (0.047, 0.1 or 0.22 µF, ESR < 0.3 Ω) between this pin and a nearby VSS pin. |
| 23 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 24 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 25 | PB12 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT1, QSPI_QSIO1 and SDIO2_D1; input voltage must not exceed 5 V. |
| 26 | PB13 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT2, QSPI_QSIO0 and SDIO2_D0; input voltage must not exceed 5 V. |
| 27 | PB14 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including VCOUT3, QSPI_QSCK and SDIO1_D6; input voltage must not exceed 5 V. |
| 28 | PB15 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including RTC_OUT, USART3_CK and SDIO1_CK; input voltage must not exceed 5 V. |
| 29 | PA8 | bidirectional | Port A general-purpose I/O (5 V tolerant) with alternate functions including MCO_1, USART1_CK, SDIO1_D1 and USBFS_SOF; input voltage must not exceed 5 V. |
| 30 | PA9/USBFS_VBUS | bidirectional | Port A general-purpose I/O (5 V tolerant) that doubles as the USB FS VBUS detection input (USBFS_VBUS); input voltage must not exceed 5 V. |
| 31 | PA10/USBFS_ID | bidirectional | Port A general-purpose I/O (5 V tolerant) that doubles as the USB FS ID input (USBFS_ID); input voltage must not exceed 5 V. |
| 32 | PA11/USBFS_DM | bidirectional | USB FS D- line of the on-chip full-speed PHY; not 5 V tolerant, input voltage must not exceed VCC+0.3 V. |
| 33 | PA12/USBFS_DP | bidirectional | USB FS D+ line of the on-chip full-speed PHY; not 5 V tolerant, input voltage must not exceed VCC+0.3 V. |
| 34 | PA13/JTMS_SWDIO | bidirectional | Port A general-purpose I/O (5 V tolerant) that serves as the JTAG TMS / SWD data pin (JTMS_SWDIO) for debug. |
| 35 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 36 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 37 | PA14/JTCK_SWCLK | input | Port A I/O (5 V tolerant) that serves as the JTAG clock / SWD clock input (JTCK_SWCLK) for debug. |
| 38 | PA15/JTDI | input | Port A I/O (5 V tolerant) that serves as the JTAG data input (JTDI) for debug. |
| 39 | PB3/JTDO_TRACESWO | output | Port B I/O that serves as the JTAG data output / trace SWO (JTDO_TRACESWO) for debug. |
| 40 | PB4/NJTRST | input | Port B I/O that serves as the active-low JTAG reset input (NJTRST) for debug. |
| 41 | PB5 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OWH, SDIO1_D3 and I2S4_EXCK; input voltage must not exceed 5 V. |
| 42 | PB6 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including ADTRG2, SDIO2_CK and I2S4_MCK; input voltage must not exceed 5 V. |
| 43 | PB7 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including ADTRG1, SDIO1_D0 and TIMA_4_PWM2; input voltage must not exceed 5 V. |
| 44 | PB11/MD | input | Mode input, fixed as input and input-only (5 V tolerant); must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC. |
| 45 | PB8 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OUL, KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS; input voltage must not exceed 5 V. |
| 46 | PB9 | bidirectional | Port B general-purpose I/O (5 V tolerant) with alternate functions including TIM4_3_OUH, SPI2_SS1, KEYOUT6 and SDIO1_D5; input voltage must not exceed 5 V. |
| 47 | VSS | power_in | Ground, 0 V reference for the device; decouple together with the VCC pins. |
| 48 | VCC | power_in | Main supply, 1.8-3.6 V; decouple with 100 nF capacitors close to the pin, plus the bulk capacitor per the power scheme. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `HC32F460JEUA-QFN48TR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm`
- 3D model: QFN-48-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `hc32f460jeua-qfn48tr-etched.step` / `hc32f460jeua-qfn48tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f460jeua-qfn48tr.step` / `hc32f460jeua-qfn48tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894261009911808) (116 pp, sha256 `df339d0329616ae4`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hc32f460jeua-qfn48tr-datasheet.pdf)