component
HC32F460JETA-LQFP48
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18d ago |
| viewers | 18d ago |
| hc32f460jeta-lqfp48-etched.glb | 18d ago |
| hc32f460jeta-lqfp48-etched.step | 18d ago |
| hc32f460jeta-lqfp48-hero.glb | 18d ago |
| hc32f460jeta-lqfp48-hero.overlay.json | 18d ago |
| hc32f460jeta-lqfp48.glb | 18d ago |
| hc32f460jeta-lqfp48.kicad_mod | 18d ago |
| hc32f460jeta-lqfp48.kicad_sym | 18d ago |
| hc32f460jeta-lqfp48.lbr | 18d ago |
| hc32f460jeta-lqfp48.step | 18d ago |
| package.json | 18d ago |
| page.json | 18d ago |
| README.md | 18d ago |
HC32F460JETA-LQFP48
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
HC32F460JETA-LQFP48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | GPIO PH2 with alternate functions EIRQ2, FCMREF, TIM4_2_CLK, EMB_IN4, SDIO2_D4 and I2S3_EXCK; digital input must not exceed 5 V, and analog input must not exceed VREFH/AVCC. |
| 2 | PC13 | bidirectional | GPIO PC13 with alternate functions EIRQ13, RTC_OUT, SDIO2_CK and I2S3_MCK; digital input must not exceed 5 V, and analog input must not exceed VREFH/AVCC. |
| 3 | PC14/XTAL32_OUT | output | XTAL32 low-speed oscillator output (32.768 kHz crystal) that is multiplexed with GPIO PC14 and EIRQ14; the crystal and load capacitors must sit close to the oscillator pins. |
| 4 | PC15/XTAL32_IN | input | XTAL32 low-speed oscillator input (32.768 kHz crystal) that is multiplexed with GPIO PC15 and EIRQ15; the crystal and load capacitors must sit close to the oscillator pins. |
| 5 | PH0/XTAL_IN | input | High-speed external oscillator input for a 4-25 MHz crystal or resonator, or a 1-25 MHz external clock in bypass mode with VIH of at least 0.8·VCC, also multiplexed with GPIO PH0 and EIRQ0. |
| 6 | PH1/XTAL_OUT | output | High-speed external oscillator output for a 4-25 MHz crystal or resonator, also multiplexed with GPIO PH1 and EIRQ1. |
| 7 | NRST | input | Active-low reset input with a minimum reset pulse width of 500 ns; connect a pull-up resistor to VCC when the pin is not used. |
| 8 | AVSS/VREFL | power_in | Analog ground, equal to VSS, which also serves as the low analog reference voltage VREFL; short it to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply equal to VCC (1.8-3.6 V), which also serves as the ADC high reference VREFH that must not exceed AVCC; short it to AVCC when the ADC is not used. |
| 10 | PA0 | bidirectional | GPIO PA0 shared with ADC1_IN0, CMP1_INP1, EIRQ0/WKUP0_0 and timer functions; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 11 | PA1 | bidirectional | GPIO PA1 shared with ADC1_IN1, CMP1_INP2, EIRQ1 and timer functions; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 12 | PA2 | bidirectional | GPIO PA2 shared with ADC1_IN2, CMP1_INP3, EIRQ2 and timer functions; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 13 | PA3 | bidirectional | GPIO PA3 shared with ADC1_IN3, PGAVSS, CMP1_INP4, EIRQ3 and timer functions; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 14 | PA4 | bidirectional | GPIO PA4 shared with ADC12_IN4, CMP2_INP1, CMP3_INP4, EIRQ4 and USART2_CK; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 15 | PA5 | bidirectional | GPIO PA5 shared with ADC12_IN5, CMP2_INP2, EIRQ5 and I2S1_MCK; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 16 | PA6 | bidirectional | GPIO PA6 shared with ADC12_IN6, CMP2_INP3, EIRQ6 and SDIO1_CMD; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 17 | PA7 | bidirectional | GPIO PA7 shared with ADC12_IN7, CMP1_INM1, CMP2_INM1, CMP3_INM1 and EIRQ7; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 18 | PB0 | bidirectional | GPIO PB0 shared with ADC12_IN8, CMP3_INP1, EIRQ0 and KEYOUT4; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 19 | PB1 | bidirectional | GPIO PB1 shared with ADC12_IN9, CMP3_INP2, EIRQ1/WKUP0_1 and QSPI_QSSN; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 20 | PB2/PVD2EXINP | bidirectional | GPIO PB2 that is also the external comparison voltage input PVD2EXINP for PVD2 and EIRQ2/WKUP0_2; digital input must not exceed 5 V and analog input must not exceed VREFH/AVCC. |
| 21 | PB10 | bidirectional | GPIO PB10 shared with EIRQ10, ADTRG2, QSPI_QSIO2 and I2S3_EXCK; digital input must not exceed 5 V. |
| 22 | VCAP_1 | power_out | Core-voltage regulator output that must be decoupled to VSS with a capacitor such as 0.1 µF or 0.22 µF (ESR < 0.3 Ω), as specified in Table 3-1 and the power-supply notes. |
| 23 | VSS | power_in | Digital power ground, 0 V reference for all supply and I/O levels. |
| 24 | VCC | power_in | Digital supply, 1.8 V to 3.6 V, decoupled close to the adjacent VSS pin. |
| 25 | PB12 | bidirectional | GPIO PB12 shared with EIRQ12, VCOUT1, QSPI_QSIO1 and SDIO2_D1; digital input must not exceed 5 V. |
| 26 | PB13 | bidirectional | GPIO PB13 shared with EIRQ13, VCOUT2, QSPI_QSIO0 and SDIO2_D0; digital input must not exceed 5 V. |
| 27 | PB14 | bidirectional | GPIO PB14 shared with EIRQ14, VCOUT3, QSPI_QSCK and SDIO1_D6; digital input must not exceed 5 V. |
| 28 | PB15 | bidirectional | GPIO PB15 shared with EIRQ15, RTC_OUT, USART3_CK and SDIO1_CK; digital input must not exceed 5 V. |
| 29 | PA8 | bidirectional | GPIO PA8 shared with EIRQ8/WKUP2_0, MCO_1, USART1_CK, SDIO1_D1 and USBFS_SOF; digital input must not exceed 5 V. |
| 30 | PA9 | bidirectional | GPIO PA9 shared with EIRQ9/WKUP2_1, SDIO1_D2 and USBFS_VBUS; digital input must not exceed 5 V. |
| 31 | PA10 | bidirectional | GPIO PA10 shared with EIRQ10/WKUP2_2, SDIO1_CD and USBFS_ID; digital input must not exceed 5 V. |
| 32 | PA11/USBFS_DM | bidirectional | USB FS D- data line (USBFS_DM) also usable as GPIO PA11; this pin is not 5 V tolerant and its input voltage must stay between −0.3 V and VCC+0.3 V. |
| 33 | PA12/USBFS_DP | bidirectional | USB FS D+ data line (USBFS_DP) also usable as GPIO PA12; this pin is not 5 V tolerant and its input voltage must stay between −0.3 V and VCC+0.3 V. |
| 34 | PA13/JTMS_SWDIO | bidirectional | SWD data I/O (JTMS_SWDIO) also usable as GPIO PA13 and EIRQ13/WKUP3_1; digital input must not exceed 5 V. |
| 35 | VSS | power_in | Digital power ground, 0 V reference for all supply and I/O levels. |
| 36 | VCC | power_in | Digital supply, 1.8 V to 3.6 V, decoupled close to the adjacent VSS pin. |
| 37 | PA14/JTCK_SWCLK | input | SWD clock / JTAG clock input (JTCK_SWCLK) also usable as GPIO PA14; digital input must not exceed 5 V. |
| 38 | PA15/JTDI | input | JTAG data input (JTDI) also usable as GPIO PA15; digital input must not exceed 5 V. |
| 39 | PB3/JTDO_TRACESWO | output | JTAG data output / trace SWO (JTDO_TRACESWO) also usable as GPIO PB3 and EIRQ3/WKUP0_3; digital input must not exceed 5 V. |
| 40 | PB4/NJTRST | input | JTAG reset input (NJTRST) also usable as GPIO PB4 and EIRQ4/WKUP1_0; digital input must not exceed 5 V. |
| 41 | PB5 | bidirectional | GPIO PB5 shared with EIRQ5/WKUP1_1, SDIO1_D3 and I2S4_EXCK; digital input must not exceed 5 V. |
| 42 | PB6 | bidirectional | GPIO PB6 shared with EIRQ6/WKUP1_2, ADTRG2, SDIO2_CK and I2S4_MCK; digital input must not exceed 5 V. |
| 43 | PB7 | bidirectional | GPIO PB7 shared with EIRQ7/WKUP1_3, ADTRG1 and SDIO1_D0; digital input must not exceed 5 V. |
| 44 | PB11/MD | input | Mode input fixed as an input that must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC; this pin is input-only and 5 V tolerant. |
| 45 | PB8 | bidirectional | GPIO PB8 shared with EIRQ8, KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS; digital input must not exceed 5 V. |
| 46 | PB9 | bidirectional | GPIO PB9 shared with EIRQ9, TIMA_6_TRIG, SPI2_SS1, KEYOUT6 and SDIO1_D5; digital input must not exceed 5 V. |
| 47 | VSS | power_in | Digital power ground, 0 V reference for all supply and I/O levels. |
| 48 | VCC | power_in | Digital supply, 1.8 V to 3.6 V, decoupled close to the adjacent VSS pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
HC32F460JETA-LQFP48 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
hc32f460jeta-lqfp48-etched.step/hc32f460jeta-lqfp48-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f460jeta-lqfp48.step/hc32f460jeta-lqfp48.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (116 pp, sha256
df339d0329616ae4, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).