HC32F460JCTA-LQFP48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F460JCTA-LQFP48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PH2	bidirectional	GPIO Port H bit 2, also EIRQ2, FCMREF, TIM4_2_CLK and SDIO2_D4; input voltage must not exceed 5 V when used as a digital input.
2	PC13	bidirectional	GPIO Port C bit 13, also EIRQ13, RTC_OUT, TIMA_4_PWM8 and SDIO2_CK; input voltage must not exceed 5 V when used as a digital input.
3	PC14/XTAL32_OUT	output	Output of the 32.768 kHz low-speed external crystal oscillator (XTAL32); also GPIO PC14 and EIRQ14.
4	PC15/XTAL32_IN	input	Input of the 32.768 kHz low-speed external crystal oscillator (XTAL32); also GPIO PC15 and EIRQ15.
5	PH0/XTAL_IN	input	Input of the main high-speed external oscillator for a 4-25 MHz crystal or resonator; also GPIO PH0 and EIRQ0.
6	PH1/XTAL_OUT	output	Output of the main high-speed external oscillator for a 4-25 MHz crystal or resonator; also GPIO PH1 and EIRQ1.
7	NRST	input	Active-low reset pin; if unused, connect a pull-up resistor to VCC.
8	AVSS/VREFL	power_in	Analog ground and ADC low reference; connect to the same potential as AVSS, and short to VSS if the analog modules are unused.
9	AVCC/VREFH	power_in	Analog supply, to be connected to the same voltage as VCC; also the ADC high reference VREFH, which must not exceed AVCC.
10	PA0/ADC1_IN0	bidirectional	GPIO Port A bit 0 with ADC1_IN0 and CMP1_INP1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
11	PA1/ADC1_IN1	bidirectional	GPIO Port A bit 1 with ADC1_IN1 and CMP1_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
12	PA2/ADC1_IN2	bidirectional	GPIO Port A bit 2 with ADC1_IN2 and CMP1_INP3 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
13	PA3/ADC1_IN3	bidirectional	GPIO Port A bit 3 with ADC1_IN3, PGAVSS and CMP1_INP4 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
14	PA4/ADC12_IN4	bidirectional	GPIO Port A bit 4 with ADC12_IN4, CMP2_INP1 and CMP3_INP4 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
15	PA5/ADC12_IN5	bidirectional	GPIO Port A bit 5 with ADC12_IN5 and CMP2_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
16	PA6/ADC12_IN6	bidirectional	GPIO Port A bit 6 with ADC12_IN6 and CMP2_INP3 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
17	PA7/ADC12_IN7	bidirectional	GPIO Port A bit 7 with ADC12_IN7 and CMP1/2/3_INM1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
18	PB0/ADC12_IN8	bidirectional	GPIO Port B bit 0 with ADC12_IN8 and CMP3_INP1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
19	PB1/ADC12_IN9	bidirectional	GPIO Port B bit 1 with ADC12_IN9 and CMP3_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V.
20	PB2/PVD2EXINP	bidirectional	GPIO Port B bit 2 that also serves as the external comparison voltage input PVD2EXINP for PVD2; digital input must not exceed 5 V.
21	PB10	bidirectional	GPIO Port B bit 10, also EIRQ10, ADTRG2, QSPI_QSIO2, SDIO1_D7 and I2S3_EXCK; digital input must not exceed 5 V.
22	VCAP_1	power_out	Core-voltage regulator node; connect a capacitor close to a VSS pin to stabilize the core voltage, using 0.1 µF or 0.22 µF on a device with only VCAP_1.
23	VSS	power_in	Ground, 0 V.
24	VCC	power_in	Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin.
25	PB12	bidirectional	GPIO Port B bit 12, also EIRQ12, VCOUT1, EMB_IN2, QSPI_QSIO1, SDIO2_D1 and I2S3_MCK; digital input must not exceed 5 V.
26	PB13	bidirectional	GPIO Port B bit 13, also EIRQ13, VCOUT2, QSPI_QSIO0 and SDIO2_D0; digital input must not exceed 5 V.
27	PB14	bidirectional	GPIO Port B bit 14, also EIRQ14, VCOUT3, QSPI_QSCK and SDIO1_D6; digital input must not exceed 5 V.
28	PB15	bidirectional	GPIO Port B bit 15, also EIRQ15, RTC_OUT, EMB_IN4, USART3_CK and SDIO1_CK; digital input must not exceed 5 V.
29	PA8	bidirectional	GPIO Port A bit 8, also EIRQ8/WKUP2_0, MCO_1, USART1_CK, SDIO1_D1 and USBFS_SOF; digital input must not exceed 5 V.
30	PA9/USBFS_VBUS	bidirectional	GPIO Port A bit 9; in USB mode it carries the USBFS_VBUS signal, and digital input must not exceed 5 V.
31	PA10/USBFS_ID	bidirectional	GPIO Port A bit 10; in USB mode it carries the USBFS_ID signal, and digital input must not exceed 5 V.
32	PA11/USBFS_DM	bidirectional	GPIO Port A bit 11 and USB FS PHY D- signal; not 5 V tolerant, so input voltage must stay between VSS−0.3 V and VCC+0.3 V.
33	PA12/USBFS_DP	bidirectional	GPIO Port A bit 12 and USB FS PHY D+ signal; not 5 V tolerant, so input voltage must stay between VSS−0.3 V and VCC+0.3 V.
34	PA13/JTMS_SWDIO	bidirectional	JTAG TMS / SWD data input-output, also GPIO PA13 and EIRQ13/WKUP3_1; digital input must not exceed 5 V.
35	VSS	power_in	Ground, 0 V.
36	VCC	power_in	Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin.
37	PA14/JTCK_SWCLK	input	JTAG clock / SWD clock input, also GPIO PA14 and EIRQ14/WKUP3_2; digital input must not exceed 5 V.
38	PA15/JTDI	input	JTAG data input JTDI, also GPIO PA15 and EIRQ15/WKUP3_3; digital input must not exceed 5 V.
39	PB3/JTDO_TRACESWO	output	JTAG data output JTDO / trace SWO output, also GPIO PB3 and EIRQ3/WKUP0_3.
40	PB4/NJTRST	input	Active-low JTAG reset input NJTRST, also GPIO PB4 and EIRQ4/WKUP1_0.
41	PB5	bidirectional	GPIO Port B bit 5, also EIRQ5/WKUP1_1, TIM4_3_OWH, SDIO1_D3 and I2S4_EXCK; digital input must not exceed 5 V.
42	PB6	bidirectional	GPIO Port B bit 6, also EIRQ6/WKUP1_2, ADTRG2, SDIO2_CK and I2S4_MCK; digital input must not exceed 5 V.
43	PB7	bidirectional	GPIO Port B bit 7, also EIRQ7/WKUP1_3, ADTRG1 and SDIO1_D0; digital input must not exceed 5 V.
44	PB11/MD	input	Mode input, fixed as input and must be held high when NRST is released; a 4.7 kΩ pull-up to VCC is recommended; also NMI and EVNTP211, and input-only per Table 2-4.
45	PB8	bidirectional	GPIO Port B bit 8, also EIRQ8, TIM4_3_OUL, KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS; digital input must not exceed 5 V.
46	PB9	bidirectional	GPIO Port B bit 9, also EIRQ9, TIM4_3_OUH, SPI2_SS1, KEYOUT6 and SDIO1_D5; digital input must not exceed 5 V.
47	VSS	power_in	Ground, 0 V.
48	VCC	power_in	Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin.

Key specifications

Parameter	Value
Manufacturer	XHSC
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating supply voltage (VCC), LQFP48 (7*7) JCTA variant	VCC	1.8		3.6	V	Ordering table, 最低/最高工作电压 column for HC32F460JCTA-LQFP48	114
Operating ambient temperature (suffix A)	TA	-40		85	°C	Suffix A = -40-85℃ industrial per part-numbering rule; decoded, not from an electrical table	11
USB FS transceiver VCC operating voltage	VCC	3		3.6	V	USB Full-Speed; functional down to 2.7 V with degraded USB electrical spec (note 2)	79
USB FS input low voltage	VIL			0.8	V	-	79
USB FS input high voltage	VIH	2			V	-	79
USB FS differential input sensitivity	VDI	0.2			V	-	79
USB FS differential common mode voltage	VCM	0.8		2.5	V	-	79
USB FS static output low voltage	VOL			0.3	V	RL=1.5kΩ to 3.6V	79
USB FS static output high voltage	VOH	2.8		3.6	V	RL=15kΩ to VSS	79
USB FS cross-over voltage	VCRS	1.3		2	V	CL=50pF	79
USB FS rise time	tR	4		20	ns	CL=50pF, 10%~90% of /VOH-VOL/	79
USB FS fall time	tF	4		20	ns	CL=50pF, 10%~90% of /VOH-VOL/	79
USB FS rise/fall time ratio	tRFMA	90		111.1	%	CL=50pF	79
USB FS pull-up resistance (idle state)	RPU	0.9	1.2	1.575	kΩ	VIN=VSS, idle state	79
USB FS pull-up resistance (device mode)	RPU	1.425	2.3	3.09	kΩ	VIN=VSS, in device mode	79
USB LS cross-over voltage	VCRS	1.3		2	V	CL=200pF~600pF	80
USB LS rise time	tR	75		300	ns	CL=200pF~600pF, 10%~90% of /VOH-VOL/	80
USB LS fall time	tF	75		300	ns	CL=200pF~600pF, 10%~90% of /VOH-VOL/	80
USB LS rise/fall time ratio	tRFMA	80		125	%	CL=200pF~600pF	80
USB LS pull-down resistance	RPD	14.25		24.8	kΩ	VIN=VCC, in host mode	80
PLL PFD input clock frequency	fPLL_IN	1		25	MHz	-	81
PLL multiplier output clock frequency	fPLL_OUT	15		240	MHz	-	81
PLL VCO output frequency	fVCO_OUT	240		480	MHz	-	81
PLL lock time	tLOCK		80	120	µs		81
USART input clock cycle (UART)	tcyc	4			tPCLK1	UART	73
USART input clock cycle (CSI)	tcyc	6			tPCLK1	CSI	73
USART input clock width	tCKw	0.4		0.6	tScyc		73
USART input clock rise time	tCKr			5	ns		73
USART input clock fall time	tCKf			5	ns		73
USART transmit delay	tTD			28	ns	CSI	73
USART receive data setup time	tRDS	15			ns	CSI	73
USART receive data hold time	tRDH	5			ns	CSI	73
I2S clock frequency	fCK	20			MHz	Master data: 32 bits	74
I2S clock frequency duty cycle	DCK	30		70	%	Slave receiver	74
WS valid time	tv(WS)	0			ns	Master mode	74
WS hold time	th(WS)	0			ns	Master mode	74
WS setup time	tsu(WS)	1			ns	Slave mode	74
Data input setup time	tsu(SD_MR)	7.5			ns	Master receiver	74
Data input setup time	tsu(SD_SR)	2			ns	Slave receiver	74
Data input hold time	th(SD_MR)	0			ns	Master receiver	74
Data output valid time	tv(SD_ST)			27	ns	Slave transmitter (after enable edge)	74
Data output valid time	tv(SD_MT)			20	ns	Master transmitter (after enable edge)	74
Data output hold time	th(SD_MT)	2.5			ns	Master transmitter (after enable edge)	74
I2C SCL clock frequency	fSCL	0		100	KHz	标准模式（SM）	76
I2C SCL clock frequency	fSCL	0		400	KHz	快速模式（FM）	76
I2C SCL low period	tLOW	4.7			us	标准模式（SM）	76
I2C SCL low period	tLOW	1.3			us	快速模式（FM）	76
I2C SCL high period	tHIGH	4			us	标准模式（SM）	76
I2C SCL high period	tHIGH	0.6			us	快速模式（FM）	76
I2C bus load capacitance	Cb			400	pF	标准模式（SM）	76

CAD (KiCad official)

Symbol: HC32F460JCTA-LQFP48
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: hc32f460jcta-lqfp48-etched.step / hc32f460jcta-lqfp48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f460jcta-lqfp48.step / hc32f460jcta-lqfp48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XHSC datasheet (116 pp, sha256 df339d0329616ae4, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# HC32F460JCTA-LQFP48

**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F460JCTA-LQFP48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | GPIO Port H bit 2, also EIRQ2, FCMREF, TIM4_2_CLK and SDIO2_D4; input voltage must not exceed 5 V when used as a digital input. |
| 2 | PC13 | bidirectional | GPIO Port C bit 13, also EIRQ13, RTC_OUT, TIMA_4_PWM8 and SDIO2_CK; input voltage must not exceed 5 V when used as a digital input. |
| 3 | PC14/XTAL32_OUT | output | Output of the 32.768 kHz low-speed external crystal oscillator (XTAL32); also GPIO PC14 and EIRQ14. |
| 4 | PC15/XTAL32_IN | input | Input of the 32.768 kHz low-speed external crystal oscillator (XTAL32); also GPIO PC15 and EIRQ15. |
| 5 | PH0/XTAL_IN | input | Input of the main high-speed external oscillator for a 4-25 MHz crystal or resonator; also GPIO PH0 and EIRQ0. |
| 6 | PH1/XTAL_OUT | output | Output of the main high-speed external oscillator for a 4-25 MHz crystal or resonator; also GPIO PH1 and EIRQ1. |
| 7 | NRST | input | Active-low reset pin; if unused, connect a pull-up resistor to VCC. |
| 8 | AVSS/VREFL | power_in | Analog ground and ADC low reference; connect to the same potential as AVSS, and short to VSS if the analog modules are unused. |
| 9 | AVCC/VREFH | power_in | Analog supply, to be connected to the same voltage as VCC; also the ADC high reference VREFH, which must not exceed AVCC. |
| 10 | PA0/ADC1_IN0 | bidirectional | GPIO Port A bit 0 with ADC1_IN0 and CMP1_INP1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 11 | PA1/ADC1_IN1 | bidirectional | GPIO Port A bit 1 with ADC1_IN1 and CMP1_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 12 | PA2/ADC1_IN2 | bidirectional | GPIO Port A bit 2 with ADC1_IN2 and CMP1_INP3 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 13 | PA3/ADC1_IN3 | bidirectional | GPIO Port A bit 3 with ADC1_IN3, PGAVSS and CMP1_INP4 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 14 | PA4/ADC12_IN4 | bidirectional | GPIO Port A bit 4 with ADC12_IN4, CMP2_INP1 and CMP3_INP4 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 15 | PA5/ADC12_IN5 | bidirectional | GPIO Port A bit 5 with ADC12_IN5 and CMP2_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 16 | PA6/ADC12_IN6 | bidirectional | GPIO Port A bit 6 with ADC12_IN6 and CMP2_INP3 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 17 | PA7/ADC12_IN7 | bidirectional | GPIO Port A bit 7 with ADC12_IN7 and CMP1/2/3_INM1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 18 | PB0/ADC12_IN8 | bidirectional | GPIO Port B bit 0 with ADC12_IN8 and CMP3_INP1 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 19 | PB1/ADC12_IN9 | bidirectional | GPIO Port B bit 1 with ADC12_IN9 and CMP3_INP2 analog input; analog input voltage must not exceed VREFH/AVCC and digital input must not exceed 5 V. |
| 20 | PB2/PVD2EXINP | bidirectional | GPIO Port B bit 2 that also serves as the external comparison voltage input PVD2EXINP for PVD2; digital input must not exceed 5 V. |
| 21 | PB10 | bidirectional | GPIO Port B bit 10, also EIRQ10, ADTRG2, QSPI_QSIO2, SDIO1_D7 and I2S3_EXCK; digital input must not exceed 5 V. |
| 22 | VCAP_1 | power_out | Core-voltage regulator node; connect a capacitor close to a VSS pin to stabilize the core voltage, using 0.1 µF or 0.22 µF on a device with only VCAP_1. |
| 23 | VSS | power_in | Ground, 0 V. |
| 24 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin. |
| 25 | PB12 | bidirectional | GPIO Port B bit 12, also EIRQ12, VCOUT1, EMB_IN2, QSPI_QSIO1, SDIO2_D1 and I2S3_MCK; digital input must not exceed 5 V. |
| 26 | PB13 | bidirectional | GPIO Port B bit 13, also EIRQ13, VCOUT2, QSPI_QSIO0 and SDIO2_D0; digital input must not exceed 5 V. |
| 27 | PB14 | bidirectional | GPIO Port B bit 14, also EIRQ14, VCOUT3, QSPI_QSCK and SDIO1_D6; digital input must not exceed 5 V. |
| 28 | PB15 | bidirectional | GPIO Port B bit 15, also EIRQ15, RTC_OUT, EMB_IN4, USART3_CK and SDIO1_CK; digital input must not exceed 5 V. |
| 29 | PA8 | bidirectional | GPIO Port A bit 8, also EIRQ8/WKUP2_0, MCO_1, USART1_CK, SDIO1_D1 and USBFS_SOF; digital input must not exceed 5 V. |
| 30 | PA9/USBFS_VBUS | bidirectional | GPIO Port A bit 9; in USB mode it carries the USBFS_VBUS signal, and digital input must not exceed 5 V. |
| 31 | PA10/USBFS_ID | bidirectional | GPIO Port A bit 10; in USB mode it carries the USBFS_ID signal, and digital input must not exceed 5 V. |
| 32 | PA11/USBFS_DM | bidirectional | GPIO Port A bit 11 and USB FS PHY D- signal; not 5 V tolerant, so input voltage must stay between VSS−0.3 V and VCC+0.3 V. |
| 33 | PA12/USBFS_DP | bidirectional | GPIO Port A bit 12 and USB FS PHY D+ signal; not 5 V tolerant, so input voltage must stay between VSS−0.3 V and VCC+0.3 V. |
| 34 | PA13/JTMS_SWDIO | bidirectional | JTAG TMS / SWD data input-output, also GPIO PA13 and EIRQ13/WKUP3_1; digital input must not exceed 5 V. |
| 35 | VSS | power_in | Ground, 0 V. |
| 36 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin. |
| 37 | PA14/JTCK_SWCLK | input | JTAG clock / SWD clock input, also GPIO PA14 and EIRQ14/WKUP3_2; digital input must not exceed 5 V. |
| 38 | PA15/JTDI | input | JTAG data input JTDI, also GPIO PA15 and EIRQ15/WKUP3_3; digital input must not exceed 5 V. |
| 39 | PB3/JTDO_TRACESWO | output | JTAG data output JTDO / trace SWO output, also GPIO PB3 and EIRQ3/WKUP0_3. |
| 40 | PB4/NJTRST | input | Active-low JTAG reset input NJTRST, also GPIO PB4 and EIRQ4/WKUP1_0. |
| 41 | PB5 | bidirectional | GPIO Port B bit 5, also EIRQ5/WKUP1_1, TIM4_3_OWH, SDIO1_D3 and I2S4_EXCK; digital input must not exceed 5 V. |
| 42 | PB6 | bidirectional | GPIO Port B bit 6, also EIRQ6/WKUP1_2, ADTRG2, SDIO2_CK and I2S4_MCK; digital input must not exceed 5 V. |
| 43 | PB7 | bidirectional | GPIO Port B bit 7, also EIRQ7/WKUP1_3, ADTRG1 and SDIO1_D0; digital input must not exceed 5 V. |
| 44 | PB11/MD | input | Mode input, fixed as input and must be held high when NRST is released; a 4.7 kΩ pull-up to VCC is recommended; also NMI and EVNTP211, and input-only per Table 2-4. |
| 45 | PB8 | bidirectional | GPIO Port B bit 8, also EIRQ8, TIM4_3_OUL, KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS; digital input must not exceed 5 V. |
| 46 | PB9 | bidirectional | GPIO Port B bit 9, also EIRQ9, TIM4_3_OUH, SPI2_SS1, KEYOUT6 and SDIO1_D5; digital input must not exceed 5 V. |
| 47 | VSS | power_in | Ground, 0 V. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple with capacitors placed close to the VSS pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage (VCC), LQFP48 (7*7) JCTA variant | VCC | 1.8 |  | 3.6 | V | Ordering table, 最低/最高工作电压 column for HC32F460JCTA-LQFP48 | 114 |
| Operating ambient temperature (suffix A) | TA | -40 |  | 85 | °C | Suffix A = -40-85℃ industrial per part-numbering rule; decoded, not from an electrical table | 11 |
| USB FS transceiver VCC operating voltage | VCC | 3 |  | 3.6 | V | USB Full-Speed; functional down to 2.7 V with degraded USB electrical spec (note 2) | 79 |
| USB FS input low voltage | VIL |  |  | 0.8 | V | - | 79 |
| USB FS input high voltage | VIH | 2 |  |  | V | - | 79 |
| USB FS differential input sensitivity | VDI | 0.2 |  |  | V | - | 79 |
| USB FS differential common mode voltage | VCM | 0.8 |  | 2.5 | V | - | 79 |
| USB FS static output low voltage | VOL |  |  | 0.3 | V | RL=1.5kΩ to 3.6V | 79 |
| USB FS static output high voltage | VOH | 2.8 |  | 3.6 | V | RL=15kΩ to VSS | 79 |
| USB FS cross-over voltage | VCRS | 1.3 |  | 2 | V | CL=50pF | 79 |
| USB FS rise time | tR | 4 |  | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 |
| USB FS fall time | tF | 4 |  | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 79 |
| USB FS rise/fall time ratio | tRFMA | 90 |  | 111.1 | % | CL=50pF | 79 |
| USB FS pull-up resistance (idle state) | RPU | 0.9 | 1.2 | 1.575 | kΩ | VIN=VSS, idle state | 79 |
| USB FS pull-up resistance (device mode) | RPU | 1.425 | 2.3 | 3.09 | kΩ | VIN=VSS, in device mode | 79 |
| USB LS cross-over voltage | VCRS | 1.3 |  | 2 | V | CL=200pF~600pF | 80 |
| USB LS rise time | tR | 75 |  | 300 | ns | CL=200pF~600pF, 10%~90% of /VOH-VOL/ | 80 |
| USB LS fall time | tF | 75 |  | 300 | ns | CL=200pF~600pF, 10%~90% of /VOH-VOL/ | 80 |
| USB LS rise/fall time ratio | tRFMA | 80 |  | 125 | % | CL=200pF~600pF | 80 |
| USB LS pull-down resistance | RPD | 14.25 |  | 24.8 | kΩ | VIN=VCC, in host mode | 80 |
| PLL PFD input clock frequency | fPLL_IN | 1 |  | 25 | MHz | - | 81 |
| PLL multiplier output clock frequency | fPLL_OUT | 15 |  | 240 | MHz | - | 81 |
| PLL VCO output frequency | fVCO_OUT | 240 |  | 480 | MHz | - | 81 |
| PLL lock time | tLOCK |  | 80 | 120 | µs |  | 81 |
| USART input clock cycle (UART) | tcyc | 4 |  |  | tPCLK1 | UART | 73 |
| USART input clock cycle (CSI) | tcyc | 6 |  |  | tPCLK1 | CSI | 73 |
| USART input clock width | tCKw | 0.4 |  | 0.6 | tScyc |  | 73 |
| USART input clock rise time | tCKr |  |  | 5 | ns |  | 73 |
| USART input clock fall time | tCKf |  |  | 5 | ns |  | 73 |
| USART transmit delay | tTD |  |  | 28 | ns | CSI | 73 |
| USART receive data setup time | tRDS | 15 |  |  | ns | CSI | 73 |
| USART receive data hold time | tRDH | 5 |  |  | ns | CSI | 73 |
| I2S clock frequency | fCK | 20 |  |  | MHz | Master data: 32 bits | 74 |
| I2S clock frequency duty cycle | DCK | 30 |  | 70 | % | Slave receiver | 74 |
| WS valid time | tv(WS) | 0 |  |  | ns | Master mode | 74 |
| WS hold time | th(WS) | 0 |  |  | ns | Master mode | 74 |
| WS setup time | tsu(WS) | 1 |  |  | ns | Slave mode | 74 |
| Data input setup time | tsu(SD_MR) | 7.5 |  |  | ns | Master receiver | 74 |
| Data input setup time | tsu(SD_SR) | 2 |  |  | ns | Slave receiver | 74 |
| Data input hold time | th(SD_MR) | 0 |  |  | ns | Master receiver | 74 |
| Data output valid time | tv(SD_ST) |  |  | 27 | ns | Slave transmitter (after enable edge) | 74 |
| Data output valid time | tv(SD_MT) |  |  | 20 | ns | Master transmitter (after enable edge) | 74 |
| Data output hold time | th(SD_MT) | 2.5 |  |  | ns | Master transmitter (after enable edge) | 74 |
| I2C SCL clock frequency | fSCL | 0 |  | 100 | KHz | 标准模式（SM） | 76 |
| I2C SCL clock frequency | fSCL | 0 |  | 400 | KHz | 快速模式（FM） | 76 |
| I2C SCL low period | tLOW | 4.7 |  |  | us | 标准模式（SM） | 76 |
| I2C SCL low period | tLOW | 1.3 |  |  | us | 快速模式（FM） | 76 |
| I2C SCL high period | tHIGH | 4 |  |  | us | 标准模式（SM） | 76 |
| I2C SCL high period | tHIGH | 0.6 |  |  | us | 快速模式（FM） | 76 |
| I2C bus load capacitance | Cb |  |  | 400 | pF | 标准模式（SM） | 76 |

## CAD (KiCad official)

- Symbol: `HC32F460JCTA-LQFP48`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `hc32f460jcta-lqfp48-etched.step` / `hc32f460jcta-lqfp48-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f460jcta-lqfp48.step` / `hc32f460jcta-lqfp48.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894451188449280) (116 pp, sha256 `df339d0329616ae4`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hc32f460jcta-lqfp48-datasheet.pdf)