HC32F452KETB-LQFP64

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

HC32F452KETB-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PH2	bidirectional	General-purpose I/O PH2 with pull-up and push-pull/open-drain output at low/medium/high drive, 5 V tolerant as a digital input; alternate functions include FCMREF and I2S3_EXCK.
2	PC13	bidirectional	General-purpose I/O PC13 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include RTC_OUT (1 Hz output) and I2S3_MCK.
3	PC14/XTAL32_OUT	output	Output of the 32.768 kHz external low-speed oscillator (XTAL32_OUT) that drives the crystal; the pin also serves as GPIO PC14 (EIRQ14) with 5 V tolerant digital input.
4	PC15/XTAL32_IN	input	Input of the 32.768 kHz external low-speed oscillator (XTAL32_IN); the pin also serves as GPIO PC15 (EIRQ15) with 5 V tolerant digital input.
5	PH0/XTAL_EXT/XTAL_OUT	bidirectional	Main oscillator pin used as XTAL_OUT for a crystal or as XTAL_EXT external clock input (1 to 25 MHz) in bypass mode; the pin also serves as GPIO PH0 (EIRQ0).
6	PH1/XTAL_IN	bidirectional	Main crystal oscillator input XTAL_IN for a 4 to 25 MHz crystal or ceramic resonator; the pin also serves as GPIO PH1 (EIRQ1).
7	NRST	input	Active-low reset input; tie to VCC through a pull-up resistor when not used, and the minimum low pulse width is 500 ns.
8	PC0/ADC12_IN10	bidirectional	General-purpose I/O PC0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN10 analog input (also CMP3_INP3) must not exceed VREFH/AVCC.
9	PC1/ADC12_IN11	bidirectional	General-purpose I/O PC1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN11 analog input must not exceed VREFH/AVCC.
10	PC2/ADC1_IN12	bidirectional	General-purpose I/O PC2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN12 analog input must not exceed VREFH/AVCC.
11	PC3/ADC1_IN13	bidirectional	General-purpose I/O PC3 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN13 analog input (also CMP1_INM2) must not exceed VREFH/AVCC.
12	AVSS/VREFL	power_in	Analog ground and low reference voltage, equal to VSS (AVSS = VSS); short to VSS when the analog modules are not used.
13	AVCC/VREFH	power_in	Analog supply equal to VCC (1.8 to 3.6 V) that also serves as ADC reference VREFH, which must not be higher than AVCC; short to AVCC when the ADC is not used.
14	PA0/ADC1_IN0	bidirectional	General-purpose I/O PA0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN0 analog input (also CMP1_INP1) must not exceed VREFH/AVCC.
15	PA1/ADC1_IN1	bidirectional	General-purpose I/O PA1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN1 analog input must not exceed VREFH/AVCC.
16	PA2/ADC1_IN2	bidirectional	General-purpose I/O PA2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN2 analog input must not exceed VREFH/AVCC.
17	PA3/ADC1_IN3	bidirectional	General-purpose I/O PA3 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN3 analog input (also PGAVSS and CMP1_INP4) must not exceed VREFH/AVCC.
18	AVSS	power_in	Analog ground, equal to VSS; connect to the ground plane with the analog decoupling capacitors.
19	AVCC	power_in	Analog supply, must be at the same voltage as VCC (1.8 to 3.6 V) and decoupled to AVSS.
20	PA4/ADC12_IN4	bidirectional	General-purpose I/O PA4 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN4 analog input (also CMP2_INP1 and CMP3_INP4) must not exceed VREFH/AVCC.
21	PA5/ADC12_IN5	bidirectional	General-purpose I/O PA5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN5 analog input (also CMP2_INP2) must not exceed VREFH/AVCC.
22	PA6/ADC12_IN6	bidirectional	General-purpose I/O PA6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN6 analog input (also CMP2_INP3) must not exceed VREFH/AVCC.
23	PA7/ADC12_IN7	bidirectional	General-purpose I/O PA7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN7 analog input (also CMP1_INM1, CMP2_INM1, CMP3_INM1) must not exceed VREFH/AVCC.
24	PC4/ADC1_IN14	bidirectional	General-purpose I/O PC4 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN14 analog input (also CMP2_INM2) must not exceed VREFH/AVCC.
25	PC5/ADC1_IN15	bidirectional	General-purpose I/O PC5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN15 analog input (also CMP3_INM2) must not exceed VREFH/AVCC.
26	PB0/ADC12_IN8	bidirectional	General-purpose I/O PB0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN8 analog input (also CMP3_INP1) must not exceed VREFH/AVCC.
27	PB1/ADC12_IN9	bidirectional	General-purpose I/O PB1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN9 analog input (also CMP3_INP2) must not exceed VREFH/AVCC.
28	PB2/PVD2EXINP	bidirectional	General-purpose I/O PB2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; it also serves as the external PVD2 comparison voltage input PVD2EXINP.
29	PB10	bidirectional	General-purpose I/O PB10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG2 and QSPI_QSIO2.
30	VCAP_1	power_out	Core-voltage pin that must be decoupled with a capacitor close to VSS; for a device with only VCAP_1 the capacitor is 0.1 µF or 0.22 µF with ESR below 0.3 Ω.
31	VSS	power_in	Ground pin at 0 V, the reference for all supply and signal voltages.
32	VCC	power_in	Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin.
33	PB12	bidirectional	General-purpose I/O PB12 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT1, QSPI_QSIO1 and I2S3_MCK.
34	PB13	bidirectional	General-purpose I/O PB13 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT2, QSPI_QSIO0 and SDIO2_D0.
35	PB14	bidirectional	General-purpose I/O PB14 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT3, QSPI_QSCK and SDIO1_D6.
36	PB15	bidirectional	General-purpose I/O PB15 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include RTC_OUT, USART3_CK and SDIO1_CK.
37	PC6	bidirectional	General-purpose I/O PC6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include QSPI_QSCK, KEYOUT3 and SDIO1_D6.
38	PC7	bidirectional	General-purpose I/O PC7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include QSPI_QSSN, KEYOUT2 and I2S2_EXCK.
39	PC8	bidirectional	General-purpose I/O PC8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include USART3_CK, KEYOUT1 and I2S2_MCK.
40	PC9	bidirectional	General-purpose I/O PC9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include MCO_2, KEYOUT0 and SDIO1_D1.
41	PA8	bidirectional	General-purpose I/O PA8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include MCO_1, USART1_CK and USBFS_SOF.
42	PA9/USBFS_VBUS	bidirectional	General-purpose I/O PA9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate function USBFS_VBUS is the USB FS VBUS signal.
43	PA10/USBFS_ID	bidirectional	General-purpose I/O PA10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate function USBFS_ID is the USB FS ID signal.
44	PA11/USBFS_DM	bidirectional	USB FS D- line of the on-chip full-speed PHY with pull-up support; this pin is not 5 V tolerant, and its input voltage must stay between VSS-0.3 V and 4.0 V.
45	PA12/USBFS_DP	bidirectional	USB FS D+ line of the on-chip full-speed PHY with pull-up support; this pin is not 5 V tolerant, and its input voltage must stay between VSS-0.3 V and 4.0 V.
46	PA13/JTMS_SWDIO	bidirectional	Serial-wire debug data pin SWDIO (JTAG TMS) that is also GPIO PA13, 5 V tolerant as a digital input.
47	VSS	power_in	Ground pin at 0 V, the reference for all supply and signal voltages.
48	VCC	power_in	Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin.
49	PA14/JTCK_SWCLK	input	Serial-wire debug clock input SWCLK (JTAG TCK) that is also GPIO PA14, 5 V tolerant as a digital input.
50	PA15/JTDI	input	JTAG data input JTDI that is also GPIO PA15, 5 V tolerant as a digital input.
51	PC10	bidirectional	General-purpose I/O PC10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_5_PWM1 and SDIO1_D2.
52	PC11	bidirectional	General-purpose I/O PC11 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_2_PWM8 and SDIO1_D3.
53	PC12	bidirectional	General-purpose I/O PC12 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_4_TRIG and SDIO1_CK.
54	PD2	bidirectional	General-purpose I/O PD2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_2_PWM4, TIMA_6_PWM6 and SDIO1_CMD.
55	PB3/JTDO_TRACESWO	output	JTAG data output JTDO / SWO trace output that is also GPIO PB3, 5 V tolerant as a digital input.
56	PB4/NJTRST	input	JTAG reset input NJTRST that is also GPIO PB4 (EIRQ4/WKUP1_0), 5 V tolerant as a digital input.
57	PB5	bidirectional	General-purpose I/O PB5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include EIRQ5/WKUP1_1, SDIO1_D3 and I2S4_EXCK.
58	PB6	bidirectional	General-purpose I/O PB6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG2, SDIO2_CK and I2S4_MCK.
59	PB7	bidirectional	General-purpose I/O PB7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG1 and SDIO1_D0.
60	PB11/MD	input	Mode input that is fixed as an input and must be held high when NRST is released; a 4.7 kΩ pull-up to VCC is recommended, and the pin is input-only and 5 V tolerant.
61	PB8	bidirectional	General-purpose I/O PB8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS.
62	PB9	bidirectional	General-purpose I/O PB9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include SPI2_SS1, KEYOUT6 and SDIO1_D5.
63	VSS	power_in	Ground pin at 0 V, the reference for all supply and signal voltages.
64	VCC	power_in	Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin.

Key specifications

Parameter	Value
Manufacturer	XHSC
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (system power)	Vcc	1.8		3.6	V		2
Operating ambient temperature range (industrial, suffix B)		-40		105	℃		12
Maximum CPU operating frequency				200	MHz		2
Input voltage on GPIO used as input function				5	V	used as input function	39
PLL PFD (Phase Frequency Detector) input clock	fPLL_IN	1		25	MHz		73
PLL multiplier output clock	fPLL_OUT	15		240	MHz		73
PLL VCO output	fVCO_OUT	240		480	MHz		73
PLL period jitter	JitterPLL	-100		100	ps	PLL PFD input clock=8MHz, System clock=120MHz, Peak-to-Peak	73
PLL cycle-to-cycle jitter	JitterPLL	-150		150	ps	PLL PFD input clock=8MHz, System clock=120MHz, Peak-to-Peak	73
PLL lock time	tLOCK		80	120	µs		73
Input clock cycle (UART)	tcyc	4			tPCLK1	UART	65
Input clock cycle (CSI)	tcyc	6				CSI	65
Input clock width	tCKw	0.4		0.6	tScyc		65
Input clock rise time	tCKr			5	ns		65
Input clock fall time	tCKf			5	ns		65
Transmit delay time (CSI)	tTD			28	ns	CSI	65
Receive data setup time (CSI)	tRDS	15			ns	CSI	65
Receive data hold time (CSI)	tRDH	5			ns	CSI	65
I2S clock frequency duty cycle	DCK	30		70	%	Slave receiver	66
WS valid time	tv(WS)	0			ns	Master mode	66
WS hold time	th(WS)	0			ns	Master mode	66
WS setup time	tsu(WS)	1			ns	Slave mode	66
Data input setup time	tsu(SD_MR)	7.5			ns	Master receiver	66
Data input setup time	tsu(SD_SR)	2			ns	Slave receiver	66
Data input hold time	th(SD_MR)	0			ns	Master receiver	66
Data output valid time	tv(SD_ST)			27	ns	Slave transmitter (after enable edge)	66
Data output valid time	tv(SD_MT)			20	ns	Master transmitter (after enable edge)	66
Data output hold time	th(SD_MT)	2.5			ns	Master transmitter (after enable edge)	66
SCL frequency	fSCL	0		100	KHz	Standard mode (SM)	68
SCL frequency	fSCL	0		400	KHz	Fast mode (FM)	68
Start/repeated start condition hold time	tHD;STA	4			us	Standard mode (SM)	68
Start/repeated start condition hold time	tHD;STA	0.6			us	Fast mode (FM)	68
SCL low period	tLOW	4.7			us	Standard mode (SM)	68
SCL low period	tLOW	1.3			us	Fast mode (FM)	68
SCL high period	tHIGH	4			us	Standard mode (SM)	68
SCL high period	tHIGH	0.6			us	Fast mode (FM)	68
Repeated start condition setup time	tSU;STA	4.7			us	Standard mode (SM)	68
Repeated start condition setup time	tSU;STA	0.6			us	Fast mode (FM)	68
Data hold time	tHD;DAT	0			us	Standard mode (SM)	68
SCL/SDA rise time	tR			1000	ns	Standard mode (SM)	68
SCL/SDA rise time	tR	6.5		300	ns	Fast mode (FM)	68
SCL/SDA fall time	tF			300	ns	Standard mode (SM)	68
SCL/SDA fall time	tF	6.5		300	ns	Fast mode (FM)	68
Stop condition setup time	tSU;STO	4			us	Standard mode (SM)	68
Stop condition setup time	tSU;STO	0.6			us	Fast mode (FM)	68
Bus free time between stop and start condition	tBUF	4.7			us	Standard mode (SM)	68
Bus free time between stop and start condition	tBUF	1.3			us	Fast mode (FM)	68
Load capacitance	Cb			400	pF	Standard mode (SM)	68
SCK clock cycle (master)	tspcyc	2			tpcyc	Master, pclk ≤60MHz	69
SCK clock cycle (slave)	tspcyc	6		4096	tpcyc	Slave	69
Data input setup time (master)	tsu	4			ns	Master, 图 3-14	69
Data input setup time (slave)	tsu	5			ns	Slave, C=30pF	69
Data input hold time (slave)	th	20			ns	Slave	69
Data output delay (master)	tod			8	ns	Master	69
Data output delay (slave)	tod			20	ns	Slave	69
SCK clock rise and fall time (master)	tsckr			5	ns	Master	69

CAD (KiCad official)

Symbol: HC32F452KETB-LQFP64
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: hc32f452ketb-lqfp64-etched.step / hc32f452ketb-lqfp64-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f452ketb-lqfp64.step / hc32f452ketb-lqfp64.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XHSC datasheet (97 pp, sha256 66fdc58cad687d2f, retrieved 2026-10-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# HC32F452KETB-LQFP64

**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

HC32F452KETB-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | General-purpose I/O PH2 with pull-up and push-pull/open-drain output at low/medium/high drive, 5 V tolerant as a digital input; alternate functions include FCMREF and I2S3_EXCK. |
| 2 | PC13 | bidirectional | General-purpose I/O PC13 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include RTC_OUT (1 Hz output) and I2S3_MCK. |
| 3 | PC14/XTAL32_OUT | output | Output of the 32.768 kHz external low-speed oscillator (XTAL32_OUT) that drives the crystal; the pin also serves as GPIO PC14 (EIRQ14) with 5 V tolerant digital input. |
| 4 | PC15/XTAL32_IN | input | Input of the 32.768 kHz external low-speed oscillator (XTAL32_IN); the pin also serves as GPIO PC15 (EIRQ15) with 5 V tolerant digital input. |
| 5 | PH0/XTAL_EXT/XTAL_OUT | bidirectional | Main oscillator pin used as XTAL_OUT for a crystal or as XTAL_EXT external clock input (1 to 25 MHz) in bypass mode; the pin also serves as GPIO PH0 (EIRQ0). |
| 6 | PH1/XTAL_IN | bidirectional | Main crystal oscillator input XTAL_IN for a 4 to 25 MHz crystal or ceramic resonator; the pin also serves as GPIO PH1 (EIRQ1). |
| 7 | NRST | input | Active-low reset input; tie to VCC through a pull-up resistor when not used, and the minimum low pulse width is 500 ns. |
| 8 | PC0/ADC12_IN10 | bidirectional | General-purpose I/O PC0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN10 analog input (also CMP3_INP3) must not exceed VREFH/AVCC. |
| 9 | PC1/ADC12_IN11 | bidirectional | General-purpose I/O PC1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN11 analog input must not exceed VREFH/AVCC. |
| 10 | PC2/ADC1_IN12 | bidirectional | General-purpose I/O PC2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN12 analog input must not exceed VREFH/AVCC. |
| 11 | PC3/ADC1_IN13 | bidirectional | General-purpose I/O PC3 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN13 analog input (also CMP1_INM2) must not exceed VREFH/AVCC. |
| 12 | AVSS/VREFL | power_in | Analog ground and low reference voltage, equal to VSS (AVSS = VSS); short to VSS when the analog modules are not used. |
| 13 | AVCC/VREFH | power_in | Analog supply equal to VCC (1.8 to 3.6 V) that also serves as ADC reference VREFH, which must not be higher than AVCC; short to AVCC when the ADC is not used. |
| 14 | PA0/ADC1_IN0 | bidirectional | General-purpose I/O PA0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN0 analog input (also CMP1_INP1) must not exceed VREFH/AVCC. |
| 15 | PA1/ADC1_IN1 | bidirectional | General-purpose I/O PA1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN1 analog input must not exceed VREFH/AVCC. |
| 16 | PA2/ADC1_IN2 | bidirectional | General-purpose I/O PA2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN2 analog input must not exceed VREFH/AVCC. |
| 17 | PA3/ADC1_IN3 | bidirectional | General-purpose I/O PA3 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN3 analog input (also PGAVSS and CMP1_INP4) must not exceed VREFH/AVCC. |
| 18 | AVSS | power_in | Analog ground, equal to VSS; connect to the ground plane with the analog decoupling capacitors. |
| 19 | AVCC | power_in | Analog supply, must be at the same voltage as VCC (1.8 to 3.6 V) and decoupled to AVSS. |
| 20 | PA4/ADC12_IN4 | bidirectional | General-purpose I/O PA4 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN4 analog input (also CMP2_INP1 and CMP3_INP4) must not exceed VREFH/AVCC. |
| 21 | PA5/ADC12_IN5 | bidirectional | General-purpose I/O PA5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN5 analog input (also CMP2_INP2) must not exceed VREFH/AVCC. |
| 22 | PA6/ADC12_IN6 | bidirectional | General-purpose I/O PA6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN6 analog input (also CMP2_INP3) must not exceed VREFH/AVCC. |
| 23 | PA7/ADC12_IN7 | bidirectional | General-purpose I/O PA7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN7 analog input (also CMP1_INM1, CMP2_INM1, CMP3_INM1) must not exceed VREFH/AVCC. |
| 24 | PC4/ADC1_IN14 | bidirectional | General-purpose I/O PC4 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN14 analog input (also CMP2_INM2) must not exceed VREFH/AVCC. |
| 25 | PC5/ADC1_IN15 | bidirectional | General-purpose I/O PC5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC1_IN15 analog input (also CMP3_INM2) must not exceed VREFH/AVCC. |
| 26 | PB0/ADC12_IN8 | bidirectional | General-purpose I/O PB0 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN8 analog input (also CMP3_INP1) must not exceed VREFH/AVCC. |
| 27 | PB1/ADC12_IN9 | bidirectional | General-purpose I/O PB1 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; ADC12_IN9 analog input (also CMP3_INP2) must not exceed VREFH/AVCC. |
| 28 | PB2/PVD2EXINP | bidirectional | General-purpose I/O PB2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; it also serves as the external PVD2 comparison voltage input PVD2EXINP. |
| 29 | PB10 | bidirectional | General-purpose I/O PB10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG2 and QSPI_QSIO2. |
| 30 | VCAP_1 | power_out | Core-voltage pin that must be decoupled with a capacitor close to VSS; for a device with only VCAP_1 the capacitor is 0.1 µF or 0.22 µF with ESR below 0.3 Ω. |
| 31 | VSS | power_in | Ground pin at 0 V, the reference for all supply and signal voltages. |
| 32 | VCC | power_in | Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin. |
| 33 | PB12 | bidirectional | General-purpose I/O PB12 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT1, QSPI_QSIO1 and I2S3_MCK. |
| 34 | PB13 | bidirectional | General-purpose I/O PB13 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT2, QSPI_QSIO0 and SDIO2_D0. |
| 35 | PB14 | bidirectional | General-purpose I/O PB14 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include VCOUT3, QSPI_QSCK and SDIO1_D6. |
| 36 | PB15 | bidirectional | General-purpose I/O PB15 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include RTC_OUT, USART3_CK and SDIO1_CK. |
| 37 | PC6 | bidirectional | General-purpose I/O PC6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include QSPI_QSCK, KEYOUT3 and SDIO1_D6. |
| 38 | PC7 | bidirectional | General-purpose I/O PC7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include QSPI_QSSN, KEYOUT2 and I2S2_EXCK. |
| 39 | PC8 | bidirectional | General-purpose I/O PC8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include USART3_CK, KEYOUT1 and I2S2_MCK. |
| 40 | PC9 | bidirectional | General-purpose I/O PC9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include MCO_2, KEYOUT0 and SDIO1_D1. |
| 41 | PA8 | bidirectional | General-purpose I/O PA8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include MCO_1, USART1_CK and USBFS_SOF. |
| 42 | PA9/USBFS_VBUS | bidirectional | General-purpose I/O PA9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate function USBFS_VBUS is the USB FS VBUS signal. |
| 43 | PA10/USBFS_ID | bidirectional | General-purpose I/O PA10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate function USBFS_ID is the USB FS ID signal. |
| 44 | PA11/USBFS_DM | bidirectional | USB FS D- line of the on-chip full-speed PHY with pull-up support; this pin is not 5 V tolerant, and its input voltage must stay between VSS-0.3 V and 4.0 V. |
| 45 | PA12/USBFS_DP | bidirectional | USB FS D+ line of the on-chip full-speed PHY with pull-up support; this pin is not 5 V tolerant, and its input voltage must stay between VSS-0.3 V and 4.0 V. |
| 46 | PA13/JTMS_SWDIO | bidirectional | Serial-wire debug data pin SWDIO (JTAG TMS) that is also GPIO PA13, 5 V tolerant as a digital input. |
| 47 | VSS | power_in | Ground pin at 0 V, the reference for all supply and signal voltages. |
| 48 | VCC | power_in | Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin. |
| 49 | PA14/JTCK_SWCLK | input | Serial-wire debug clock input SWCLK (JTAG TCK) that is also GPIO PA14, 5 V tolerant as a digital input. |
| 50 | PA15/JTDI | input | JTAG data input JTDI that is also GPIO PA15, 5 V tolerant as a digital input. |
| 51 | PC10 | bidirectional | General-purpose I/O PC10 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_5_PWM1 and SDIO1_D2. |
| 52 | PC11 | bidirectional | General-purpose I/O PC11 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_2_PWM8 and SDIO1_D3. |
| 53 | PC12 | bidirectional | General-purpose I/O PC12 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_4_TRIG and SDIO1_CK. |
| 54 | PD2 | bidirectional | General-purpose I/O PD2 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include TIMA_2_PWM4, TIMA_6_PWM6 and SDIO1_CMD. |
| 55 | PB3/JTDO_TRACESWO | output | JTAG data output JTDO / SWO trace output that is also GPIO PB3, 5 V tolerant as a digital input. |
| 56 | PB4/NJTRST | input | JTAG reset input NJTRST that is also GPIO PB4 (EIRQ4/WKUP1_0), 5 V tolerant as a digital input. |
| 57 | PB5 | bidirectional | General-purpose I/O PB5 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include EIRQ5/WKUP1_1, SDIO1_D3 and I2S4_EXCK. |
| 58 | PB6 | bidirectional | General-purpose I/O PB6 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG2, SDIO2_CK and I2S4_MCK. |
| 59 | PB7 | bidirectional | General-purpose I/O PB7 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include ADTRG1 and SDIO1_D0. |
| 60 | PB11/MD | input | Mode input that is fixed as an input and must be held high when NRST is released; a 4.7 kΩ pull-up to VCC is recommended, and the pin is input-only and 5 V tolerant. |
| 61 | PB8 | bidirectional | General-purpose I/O PB8 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include KEYOUT7, SDIO1_D4 and USBFS_DRVVBUS. |
| 62 | PB9 | bidirectional | General-purpose I/O PB9 with pull-up and push-pull/open-drain output, 5 V tolerant as a digital input; alternate functions include SPI2_SS1, KEYOUT6 and SDIO1_D5. |
| 63 | VSS | power_in | Ground pin at 0 V, the reference for all supply and signal voltages. |
| 64 | VCC | power_in | Power supply pin, 1.8 V to 3.6 V, to be decoupled to a nearby VSS pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (system power) | Vcc | 1.8 |  | 3.6 | V |  | 2 |
| Operating ambient temperature range (industrial, suffix B) |  | -40 |  | 105 | ℃ |  | 12 |
| Maximum CPU operating frequency |  |  |  | 200 | MHz |  | 2 |
| Input voltage on GPIO used as input function |  |  |  | 5 | V | used as input function | 39 |
| PLL PFD (Phase Frequency Detector) input clock | fPLL_IN | 1 |  | 25 | MHz |  | 73 |
| PLL multiplier output clock | fPLL_OUT | 15 |  | 240 | MHz |  | 73 |
| PLL VCO output | fVCO_OUT | 240 |  | 480 | MHz |  | 73 |
| PLL period jitter | JitterPLL | -100 |  | 100 | ps | PLL PFD input clock=8MHz, System clock=120MHz, Peak-to-Peak | 73 |
| PLL cycle-to-cycle jitter | JitterPLL | -150 |  | 150 | ps | PLL PFD input clock=8MHz, System clock=120MHz, Peak-to-Peak | 73 |
| PLL lock time | tLOCK |  | 80 | 120 | µs |  | 73 |
| Input clock cycle (UART) | tcyc | 4 |  |  | tPCLK1 | UART | 65 |
| Input clock cycle (CSI) | tcyc | 6 |  |  |  | CSI | 65 |
| Input clock width | tCKw | 0.4 |  | 0.6 | tScyc |  | 65 |
| Input clock rise time | tCKr |  |  | 5 | ns |  | 65 |
| Input clock fall time | tCKf |  |  | 5 | ns |  | 65 |
| Transmit delay time (CSI) | tTD |  |  | 28 | ns | CSI | 65 |
| Receive data setup time (CSI) | tRDS | 15 |  |  | ns | CSI | 65 |
| Receive data hold time (CSI) | tRDH | 5 |  |  | ns | CSI | 65 |
| I2S clock frequency duty cycle | DCK | 30 |  | 70 | % | Slave receiver | 66 |
| WS valid time | tv(WS) | 0 |  |  | ns | Master mode | 66 |
| WS hold time | th(WS) | 0 |  |  | ns | Master mode | 66 |
| WS setup time | tsu(WS) | 1 |  |  | ns | Slave mode | 66 |
| Data input setup time | tsu(SD_MR) | 7.5 |  |  | ns | Master receiver | 66 |
| Data input setup time | tsu(SD_SR) | 2 |  |  | ns | Slave receiver | 66 |
| Data input hold time | th(SD_MR) | 0 |  |  | ns | Master receiver | 66 |
| Data output valid time | tv(SD_ST) |  |  | 27 | ns | Slave transmitter (after enable edge) | 66 |
| Data output valid time | tv(SD_MT) |  |  | 20 | ns | Master transmitter (after enable edge) | 66 |
| Data output hold time | th(SD_MT) | 2.5 |  |  | ns | Master transmitter (after enable edge) | 66 |
| SCL frequency | fSCL | 0 |  | 100 | KHz | Standard mode (SM) | 68 |
| SCL frequency | fSCL | 0 |  | 400 | KHz | Fast mode (FM) | 68 |
| Start/repeated start condition hold time | tHD;STA | 4 |  |  | us | Standard mode (SM) | 68 |
| Start/repeated start condition hold time | tHD;STA | 0.6 |  |  | us | Fast mode (FM) | 68 |
| SCL low period | tLOW | 4.7 |  |  | us | Standard mode (SM) | 68 |
| SCL low period | tLOW | 1.3 |  |  | us | Fast mode (FM) | 68 |
| SCL high period | tHIGH | 4 |  |  | us | Standard mode (SM) | 68 |
| SCL high period | tHIGH | 0.6 |  |  | us | Fast mode (FM) | 68 |
| Repeated start condition setup time | tSU;STA | 4.7 |  |  | us | Standard mode (SM) | 68 |
| Repeated start condition setup time | tSU;STA | 0.6 |  |  | us | Fast mode (FM) | 68 |
| Data hold time | tHD;DAT | 0 |  |  | us | Standard mode (SM) | 68 |
| SCL/SDA rise time | tR |  |  | 1000 | ns | Standard mode (SM) | 68 |
| SCL/SDA rise time | tR | 6.5 |  | 300 | ns | Fast mode (FM) | 68 |
| SCL/SDA fall time | tF |  |  | 300 | ns | Standard mode (SM) | 68 |
| SCL/SDA fall time | tF | 6.5 |  | 300 | ns | Fast mode (FM) | 68 |
| Stop condition setup time | tSU;STO | 4 |  |  | us | Standard mode (SM) | 68 |
| Stop condition setup time | tSU;STO | 0.6 |  |  | us | Fast mode (FM) | 68 |
| Bus free time between stop and start condition | tBUF | 4.7 |  |  | us | Standard mode (SM) | 68 |
| Bus free time between stop and start condition | tBUF | 1.3 |  |  | us | Fast mode (FM) | 68 |
| Load capacitance | Cb |  |  | 400 | pF | Standard mode (SM) | 68 |
| SCK clock cycle (master) | tspcyc | 2 |  |  | tpcyc | Master, pclk ≤60MHz | 69 |
| SCK clock cycle (slave) | tspcyc | 6 |  | 4096 | tpcyc | Slave | 69 |
| Data input setup time (master) | tsu | 4 |  |  | ns | Master, 图 3-14 | 69 |
| Data input setup time (slave) | tsu | 5 |  |  | ns | Slave, C=30pF | 69 |
| Data input hold time (slave) | th | 20 |  |  | ns | Slave | 69 |
| Data output delay (master) | tod |  |  | 8 | ns | Master | 69 |
| Data output delay (slave) | tod |  |  | 20 | ns | Slave | 69 |
| SCK clock rise and fall time (master) | tsckr |  |  | 5 | ns | Master | 69 |

## CAD (KiCad official)

- Symbol: `HC32F452KETB-LQFP64`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `hc32f452ketb-lqfp64-etched.step` / `hc32f452ketb-lqfp64-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f452ketb-lqfp64.step` / `hc32f452ketb-lqfp64.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590457748766171136) (97 pp, sha256 `66fdc58cad687d2f`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hc32f452ketb-lqfp64-datasheet.pdf)