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HC32F451JEUB-QFN48TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), QFN-48(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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HC32F451JEUB-QFN48TR
XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48(5x5)
HC32F451JEUB-QFN48TR from XHSC, in a QFN-48(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | General-purpose I/O PH2 with pull-up, push-pull or open-drain output and low/medium/high drive, 5 V tolerant as a digital input; alternate functions include EIRQ2 and SDIO2_D4/I2S3_EXCK. |
| 2 | PC13 | bidirectional | General-purpose I/O PC13 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as a digital input; alternate functions include EIRQ13, RTC_OUT and I2S3_MCK. |
| 3 | PC14/XTAL32_OUT | output | Output of the 32.768 kHz low-speed crystal oscillator (XTAL32) that must be loaded with capacitors CL1/CL2 close to the pin; the pin can also be used as GPIO PC14 with EIRQ14. |
| 4 | PC15/XTAL32_IN | input | Input of the 32.768 kHz low-speed crystal oscillator (XTAL32), with capacitors CL1/CL2 placed as close as possible to the oscillator pins; the pin can also be used as GPIO PC15 with EIRQ15. |
| 5 | PH0/XTAL_EXT/XTAL_OUT | bidirectional | High-speed external clock pin: XTAL_EXT external clock input (1-25 MHz, 40-60 % duty, 5 ns max rise/fall) in bypass mode, or XTAL_OUT of the 4-25 MHz crystal oscillator; the pin can also be used as GPIO PH0 with EIRQ0. |
| 6 | PH1/XTAL_IN | bidirectional | Input of the 4-25 MHz high-speed crystal/ceramic resonator oscillator (XTAL_IN), with load capacitors placed close to the oscillator pins; the pin can also be used as GPIO PH1 with EIRQ1. |
| 7 | NRST | input | Active-low reset input; keep it pulled up to VCC through a resistor when not used, and the reset low pulse must be at least 500 ns. |
| 8 | AVSS/VREFL | power_in | Analog ground and low reference voltage, which must be at the same potential as VSS; tie it to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply 1.8-3.6 V that must equal VCC, and the ADC high reference VREFH that must not exceed AVCC (VAVCC-VREFH must be below 1.2 V); tie it to AVCC when the ADC is not used. |
| 10 | PA0/ADC1_IN0 | bidirectional | General-purpose I/O PA0 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC1_IN0 analog input its voltage must not exceed VREFH/AVCC. |
| 11 | PA1/ADC1_IN1 | bidirectional | General-purpose I/O PA1 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC1_IN1 analog input its voltage must not exceed VREFH/AVCC. |
| 12 | PA2/ADC1_IN2 | bidirectional | General-purpose I/O PA2 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC1_IN2 analog input its voltage must not exceed VREFH/AVCC. |
| 13 | PA3/ADC1_IN3 | bidirectional | General-purpose I/O PA3 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC1_IN3 analog input its voltage must not exceed VREFH/AVCC. |
| 14 | PA4/ADC12_IN4 | bidirectional | General-purpose I/O PA4 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN4 analog input its voltage must not exceed VREFH/AVCC. |
| 15 | PA5/ADC12_IN5 | bidirectional | General-purpose I/O PA5 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN5 analog input its voltage must not exceed VREFH/AVCC. |
| 16 | PA6/ADC12_IN6 | bidirectional | General-purpose I/O PA6 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN6 analog input its voltage must not exceed VREFH/AVCC. |
| 17 | PA7/ADC12_IN7 | bidirectional | General-purpose I/O PA7 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN7 analog input its voltage must not exceed VREFH/AVCC. |
| 18 | PB0/ADC12_IN8 | bidirectional | General-purpose I/O PB0 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN8 analog input its voltage must not exceed VREFH/AVCC. |
| 19 | PB1/ADC12_IN9 | bidirectional | General-purpose I/O PB1 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; as ADC12_IN9 analog input its voltage must not exceed VREFH/AVCC. |
| 20 | PB2/PVD2EXINP | bidirectional | General-purpose I/O PB2 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; when PVD2 is set to external input mode this pin is the PVD2EXINP comparison voltage input. |
| 21 | PB10 | bidirectional | General-purpose I/O PB10 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ10, ADTRG2 and I2S3_EXCK. |
| 22 | VCAP_1 | passive | Core voltage decoupling pin: connect a 0.1 µF or 0.22 µF capacitor (ESR < 0.3 Ω) close to a VSS pin to stabilize the core voltage. |
| 23 | VSS | power_in | Ground pin; 0 V reference for the device supply, to be connected to the external ground. |
| 24 | VCC | power_in | Main supply pin, 1.8 V to 3.6 V, decoupled with capacitors close to the adjacent VSS pin (one 4.7 µF ceramic capacitor must be connected to a VCC pin). |
| 25 | PB12 | bidirectional | General-purpose I/O PB12 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ12, VCOUT1 and I2S3_MCK. |
| 26 | PB13 | bidirectional | General-purpose I/O PB13 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ13, VCOUT2 and QSPI_QSIO0. |
| 27 | PB14 | bidirectional | General-purpose I/O PB14 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ14, VCOUT3 and QSPI_QSCK. |
| 28 | PB15 | bidirectional | General-purpose I/O PB15 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ15, RTC_OUT and USART3_CK. |
| 29 | PA8 | bidirectional | General-purpose I/O PA8 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ8/WKUP2_0, MCO_1 and USBFS_SOF. |
| 30 | PA9/USBFS_VBUS | bidirectional | General-purpose I/O PA9 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate function USBFS_VBUS is the USB FS VBUS signal input. |
| 31 | PA10/USBFS_ID | bidirectional | General-purpose I/O PA10 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate function USBFS_ID is the USB FS ID signal. |
| 32 | PA11/USBFS_DM | bidirectional | USB FS D- signal (on-chip full-speed PHY) that is not 5 V tolerant and whose input voltage must stay between VSS-0.3 V and 4.0 V; it supports pull-up and push-pull/open-drain output with selectable drive. |
| 33 | PA12/USBFS_DP | bidirectional | USB FS D+ signal (on-chip full-speed PHY) that is not 5 V tolerant and whose input voltage must stay between VSS-0.3 V and 4.0 V; it supports pull-up and push-pull/open-drain output with selectable drive. |
| 34 | PA13/JTMS_SWDIO | bidirectional | General-purpose I/O PA13 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; in debug mode this pin is the JTMS/SWDIO serial-wire debug data line. |
| 35 | VSS | power_in | Ground pin; 0 V reference for the device supply, to be connected to the external ground. |
| 36 | VCC | power_in | Main supply pin, 1.8 V to 3.6 V, decoupled with capacitors close to the adjacent VSS pin. |
| 37 | PA14/JTCK_SWCLK | bidirectional | General-purpose I/O PA14 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; in debug mode this pin is the JTCK/SWCLK serial-wire clock input. |
| 38 | PA15/JTDI | bidirectional | General-purpose I/O PA15 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; in debug mode this pin is the JTDI JTAG data input. |
| 39 | PB3/JTDO_TRACESWO | bidirectional | General-purpose I/O PB3 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; in debug mode this pin is the JTDO/TRACESWO output. |
| 40 | PB4/NJTRST | bidirectional | General-purpose I/O PB4 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; in debug mode this pin is the NJTRST JTAG reset input. |
| 41 | PB5 | bidirectional | General-purpose I/O PB5 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ5/WKUP1_1, SDIO1_D3 and I2S4_EXCK. |
| 42 | PB6 | bidirectional | General-purpose I/O PB6 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ6/WKUP1_2, ADTRG2 and I2S4_MCK. |
| 43 | PB7 | bidirectional | General-purpose I/O PB7 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ7/WKUP1_3, ADTRG1 and SDIO1_D0. |
| 44 | PB11/MD | input | Mode input fixed as an input-only pin that must be held high when NRST is released, with a recommended 4.7 kΩ pull-up to VCC; it is 5 V tolerant and has no output function. |
| 45 | PB8 | bidirectional | General-purpose I/O PB8 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ8, KEYOUT7 and USBFS_DRVVBUS. |
| 46 | PB9 | bidirectional | General-purpose I/O PB9 with pull-up, push-pull or open-drain output and selectable drive, 5 V tolerant as digital input; alternate functions include EIRQ9, SPI2_SS1 and KEYOUT6. |
| 47 | VSS | power_in | Ground pin; 0 V reference for the device supply, to be connected to the external ground. |
| 48 | VCC | power_in | Main supply pin, 1.8 V to 3.6 V, decoupled with capacitors close to the adjacent VSS pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 系统电源（Vcc）工作电压 / Supply voltage | VCC | 1.8 | 3.6 | V | 12 | ||
| 环境温度范围 / Operating temperature range (B: industrial) | -40 | 105 | ℃ | 12 | |||
| PLL PFD input clock | fPLL_IN | 1 | 25 | MHz | 73 | ||
| PLL multiplier output clock | fPLL_OUT | 15 | 240 | MHz | 73 | ||
| PLL VCO output | fVCO_OUT | 240 | 480 | MHz | 73 | ||
| PLL lock time | tLOCK | 80 | 120 | µs | 73 | ||
| USB FS 工作电压 / VCC | VCC | 3 | 3.6 | V | 71 | ||
| USB FS 输入低电平 | VIL | 0.8 | V | 71 | |||
| USB FS 输入高电平 | VIH | 2 | V | 71 | |||
| USB FS 差分输入灵敏度 | VDI | 0.2 | V | 71 | |||
| USB FS 差分共模电压 | VCM | 0.8 | 2.5 | V | 71 | ||
| USB FS 静态输出低电平 | VOL | 0.3 | V | RL=1.5kΩ to 3.6V | 71 | ||
| USB FS 静态输出高电平 | VOH | 2.8 | 3.6 | V | RL=15kΩ to VSS | 71 | |
| USB FS Cross-over电压 | VCRS | 1.3 | 2 | V | CL=50pF | 71 | |
| USB FS 上升时间 | tR | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 71 | |
| USB FS 下降时间 | tF | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 71 | |
| USB FS 上升下降时间比 | tRFMA | 90 | 111.1 | % | CL=50pF | 71 | |
| USB FS 上拉电阻 (idle state) | RPU | 0.9 | 1.2 | 1.575 | kΩ | VIN= VSS, idle state | 71 |
| USB FS 上拉电阻 (device mode) | RPU | 1.425 | 2.3 | 3.09 | kΩ | VIN= VSS, in device mode | 71 |
| USB LS 工作电压 / VCC | VCC | 3 | 3.6 | V | 72 | ||
| USB LS 输入低电平 | VIL | 0.8 | V | 72 | |||
| USB LS 输入高电平 | VIH | 2 | V | 72 | |||
| USB LS 差分输入灵敏度 | VDI | 0.2 | V | 72 | |||
| USB LS 差分共模电压 | VCM | 0.8 | 2.5 | V | 72 | ||
| USB LS 静态输出低电平 | VOL | 0.3 | V | RL=1.5kΩ to 3.6V | 72 | ||
| USB LS 静态输出高电平 | VOH | 2.8 | 3.6 | V | RL=15kΩ to VSS | 72 | |
| USB LS Cross-over电压 | VCRS | 1.3 | 2 | V | CL=200pF~600pF | 72 | |
| USB LS 上升时间 | tR | 75 | 300 | ns | CL=200pF~600pF, 10%~90% of /VOH-VOL/ | 72 | |
| USB LS 下降时间 | tF | 75 | 300 | ns | CL=200pF~600pF, 10%~90% of /VOH-VOL/ | 72 | |
| USB LS 上升下降时间比 | tRFMA | 80 | 125 | % | CL=200pF~600pF | 72 | |
| USB LS 下拉电阻 | RPD | 14.25 | 24.8 | kΩ | VIN= VCC, in host mode | 72 | |
| UART 输入时钟周期数 | tcyc | 4 | tPCLK1 | UART | 65 | ||
| CSI 输入时钟周期数 | tcyc | 6 | CSI | 65 | |||
| 输入时钟宽度 | tCKw | 0.4 | 0.6 | tScyc | 65 | ||
| 输入时钟上升时间 | tCKr | 5 | ns | 65 | |||
| 输入时钟下降时间 | tCKf | 5 | ns | 65 | |||
| 发送延迟时间 | tTD | 28 | ns | CSI | 65 | ||
| 接收数据建立时间 | tRDS | 15 | ns | CSI | 65 | ||
| 接收数据保持时间 | tRDH | 5 | ns | CSI | 65 | ||
| I2S clock frequency duty cycle | DCK | 30 | 70 | % | Slave receiver | 66 | |
| WS valid time | tv(WS) | 0 | ns | Master mode | 66 | ||
| WS hold time | th(WS) | 0 | ns | Master mode | 66 | ||
| WS setup time | tsu(WS) | 1 | ns | Slave mode | 66 | ||
| Data input setup time | tsu(SD_MR) | 7.5 | ns | Master receiver | 66 | ||
| Data input setup time | tsu(SD_SR) | 2 | ns | Slave receiver | 66 | ||
| Data input hold time | th(SD_MR) | 0 | ns | Master receiver | 66 | ||
| Data output valid time | tv(SD_ST) | 27 | ns | Slave transmitter (after enable edge) | 66 | ||
| Data output valid time | tv(SD_MT) | 20 | ns | Master transmitter (after enable edge) | 66 | ||
| Data output hold time | th(SD_MT) | 2.5 | ns | Master transmitter (after enable edge) | 66 | ||
| I2C SCL frequency | fSCL | 0 | 100 | KHz | Standard mode (SM) | 68 | |
| I2C SCL frequency | fSCL | 0 | 400 | KHz | Fast mode (FM) | 68 | |
| I2C 开始/重新开始条件保持时间 | tHD;STA | 4 | us | Standard mode (SM) | 68 | ||
| I2C SCL低电平时间 | tLOW | 4.7 | us | Standard mode (SM) | 68 | ||
| I2C SCL低电平时间 | tLOW | 1.3 | us | Fast mode (FM) | 68 | ||
| I2C SCL高电平时间 | tHIGH | 4 | us | Standard mode (SM) | 68 | ||
| I2C SCL高电平时间 | tHIGH | 0.6 | us | Fast mode (FM) | 68 | ||
| I2C 重新开始条件建立时间 | tSU;STA | 4.7 | us | Standard mode (SM) | 68 | ||
| I2C 重新开始条件建立时间 | tSU;STA | 0.6 | us | Fast mode (FM) | 68 |
CAD (KiCad official)
- Symbol:
HC32F451JEUB-QFN48TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm - 3D model: QFN-48(5x5) (KiCad packages3D, STEP)
- 3D model files:
hc32f451jeub-qfn48tr-etched.step/hc32f451jeub-qfn48tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f451jeub-qfn48tr.step/hc32f451jeub-qfn48tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (97 pp, sha256
66fdc58cad687d2f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).