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HC32F448JATI-LQ48

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HC32F448JATI-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F448JATI-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PH2/FG2 bidirectional GPIO PH2 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
2 PC13/FG2 bidirectional GPIO PC13 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
3 PC14/XTAL32_IN input Input of the external 32.768 kHz sub-clock (XTAL32) oscillator; the pin is also a 5 V tolerant GPIO.
4 PC15/XTAL32_OUT output Output of the external 32.768 kHz sub-clock (XTAL32) oscillator; the pin is also a 5 V tolerant GPIO.
5 PH0/XTAL_IN input External main oscillator (XTAL) interface input for a 4-25 MHz crystal or resonator; the pin is also a 5 V tolerant GPIO.
6 PH1/XTAL_EXT/XTAL_OUT bidirectional External main clock input (XTAL_EXT, 1-25 MHz in bypass mode) or external main oscillator output (XTAL_OUT); the pin is also a 5 V tolerant GPIO.
7 NRST input Active-low reset input; if unused, connect a pull-up resistor to VCC.
8 AVSS/VREFL power_in Analog ground and low reference voltage; connect to VSS when no separate analog supply is used and do not leave floating.
9 AVCC/VREFH power_in Analog supply at the same voltage as VCC (1.8-3.6 V) and high reference voltage; connect to VCC when no separate analog supply is used and do not leave floating.
10 PA0/ADC1_IN0/FG1 bidirectional GPIO PA0 with ADC1 analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
11 PA1/ADC1_IN1/FG1 bidirectional GPIO PA1 with ADC1 analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
12 PA2/ADC1_IN2/FG1 bidirectional GPIO PA2 with ADC1 analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
13 PA3/ADC1_IN3/FG1 bidirectional GPIO PA3 with ADC1 analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
14 PA4/ADC12_IN4/FG1 bidirectional GPIO PA4 with ADC1/ADC2 analog input and DAC_OUT1 output; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
15 PA5/ADC12_IN5/FG1 bidirectional GPIO PA5 with ADC1/ADC2 analog input and DAC_OUT2 output; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
16 PA6/ADC123_IN6/FG1 bidirectional GPIO PA6 with ADC1/2/3 shared analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
17 PA7/ADC123_IN7/FG1 bidirectional GPIO PA7 with ADC1/2/3 shared analog input; not 5 V tolerant, so the input must not exceed VCC (and the absolute maximum is VCC+0.7 V).
18 PB0/ADC123_IN8/FG1 bidirectional GPIO PB0 with ADC1/2/3 shared analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
19 PB1/ADC123_IN9/FG1 bidirectional GPIO PB1 with ADC1/2/3 shared analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
20 PB2/PVD2EXINP/FG1 bidirectional GPIO PB2 with PVD2 external comparison voltage input (PVD2EXINP); 5 V tolerant, input not to exceed 5 V.
21 PB10/ADC3_IN11/FG2 bidirectional GPIO PB10 with ADC3 analog input; 5 V tolerant, and analog input voltage must not exceed VREFH/AVCC.
22 VCAP_1 passive Core voltage pin; connect a capacitor close to VSS to stabilize the core voltage, with total capacitance of 0.094/0.1 µF or 0.2/0.22 µF that must match the PWC_PWRC1.PDTS setting.
23 VSS power_in Power ground, 0 V.
24 VCC power_in Main power supply, 1.8 V to 3.6 V; decouple close to VSS with the capacitors specified in the power scheme.
25 PB12/FG2 bidirectional GPIO PB12 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
26 PB13/FG2 bidirectional GPIO PB13 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
27 PB14/FG2 bidirectional GPIO PB14 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
28 PB15/FG2 bidirectional GPIO PB15 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
29 PA8/FG1 bidirectional GPIO PA8 (function group FG1) with CMP4_INM2 input; not 5 V tolerant, so the input must not exceed VCC.
30 PA9/FG1 bidirectional GPIO PA9 (function group FG1), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
31 PA10/FG1 bidirectional GPIO PA10 (function group FG1), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
32 PA11/FG1 bidirectional GPIO PA11 (function group FG1), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
33 PA12/FG1 bidirectional GPIO PA12 (function group FG1), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
34 PA13/JTMS_SWDIO/FG1 bidirectional SWD data I/O (JTMS_SWDIO) multiplexed on GPIO PA13; 5 V tolerant with input not to exceed 5 V.
35 VSS power_in Power ground, 0 V.
36 VCC power_in Main power supply, 1.8 V to 3.6 V; decouple close to VSS with the capacitors specified in the power scheme.
37 PA14/JTCK_SWCLK/FG1 input SWD clock / JTAG clock (JTCK_SWCLK) multiplexed on GPIO PA14; 5 V tolerant with input not to exceed 5 V.
38 PA15/JTDI/FG1 input JTAG data input (JTDI) multiplexed on GPIO PA15; 5 V tolerant with input not to exceed 5 V.
39 PB3/JTDO_SWO/FG2 output JTAG data output / SWO trace output (JTDO_TRACESWO) multiplexed on GPIO PB3; 5 V tolerant GPIO.
40 PB4/JTRST/FG2 input JTAG reset input (NJTRST) multiplexed on GPIO PB4; 5 V tolerant GPIO.
41 PB5/FG2 bidirectional GPIO PB5 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
42 PB6/FG2 bidirectional GPIO PB6 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
43 PB7/FG2 bidirectional GPIO PB7 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
44 PB11/MD input Mode input; must be held low when NRST is released (low-to-high), and a 4.7 kΩ pull-down to VSS is recommended; the pin is also a 5 V tolerant GPIO.
45 PB8/FG2 bidirectional GPIO PB8 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
46 PB9/FG2 bidirectional GPIO PB9 (function group FG2), 5 V tolerant with input not to exceed 5 V, supporting pull-up/pull-down, push-pull/open-drain output and low/medium/high drive.
47 VSS power_in Power ground, 0 V.
48 VCC power_in Main power supply, 1.8 V to 3.6 V; decouple close to VSS with the capacitors specified in the power scheme.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
系统电源电压（标准工作电压） VCC 1.8 3.6 V 41
模拟工作电压 VAVCC 1.8 3.6 V 41
内部 AHB 时钟频率（高速模式） fHCLK 200 MHz PWRC2.DVS=0b11, PWRC3.DDAS=0b1111 41
内部 AHB 时钟频率（超低速模式） fHCLK 8 MHz PWRC2.DVS=0b10, PWRC3.DDAS=0b0000 41
5V耐压引脚输入电压 VIN -0.3 5.5 V 2V≤VCC≤3.6V, 2V≤VAVCC≤3.6V 41
5V耐压引脚输入电压 VIN -0.3 5.2 V VCC<2V, VAVCC<2V 41
非5V耐压引脚输入电压（PA7/PA8/PC3~5） VIN -0.3 V 上限为 VCC+0.3（表达式） 41
结温范围 TJ -40 125 °C 41
工作温度范围 TA -40 105 °C 41
VCC 上升时间速率 tVCC 20 20000 µs/V 41
VCC 下降时间速率 tVCC 20 20000 µs/V 41
外部主电源电压（VCC、AVCC） VCC-VSS -0.3 4 V 40
除 PA7、PA8、PC3~PC5 外引脚输入电压 VIN 5.8 V 上限 VCC+4.0，最大 5.8V；下限 VSS-0.3 40
PA7、PA8、PC3~PC5 引脚输入电压 VIN 4 V 上限 VCC+0.7，最大 4.0V；下限 VSS-0.3 40
不同接地引脚之间的电压差 /VSSx-VSS/ 50 mV 40
流入所有 VCCx 电源线的总电流（拉电流） ∑IVCC 240 mA 40
流出所有 VSSx 接地线的总电流（灌电流） ∑IVSS -240 mA 40
流入每个 VCCx 电源线的最大电流（拉电流） IVCC 100 mA 40
流出每个 VSSx 接地线的最大电流（灌电流） IVSS -100 mA 40
任意 I/O 和控制引脚输出灌电流 IIO 20 mA 40
任意 I/O 和控制引脚输出拉电流 IIO -20 mA 40
所有 I/O 和控制引脚总输出灌电流（48PINs 封装） ∑IIO 80 mA 48PINs 封装 40
所有 I/O 和控制引脚总输出拉电流（48PINs 封装） ∑IIO -80 mA 48PINs 封装 40
储存温度范围 TSTG -65 150 ℃ 40
最大结温范围 TJ -40 125 ℃ 40
BOR 监测电压 VBOR 1.7 1.9 2.1 V ICG1.BOR_LEV[1:0]=0b00 42
BOR 监测电压 VBOR 2.1 2.3 2.5 V ICG1.BOR_LEV[1:0]=0b11 42
上电复位阈值（上升沿） VPOR 1.56 1.68 1.8 V 上升沿 42
掉电复位阈值（下降沿） VPDR 1.52 1.64 1.76 V 下降沿 42
PVD1 监测电压 VPVD1 1.8 2 2.2 V PVD1LVL[2:0]=0b000 42
PVD1 监测电压 VPVD1 2.73 2.95 3.17 V PVD1LVL[2:0]=0b111 42
PVD2 监测电压 VPVD2 1.9 2.1 2.3 V PVD2LVL[2:0]=0b000 42
PVD2 监测电压 VPVD2 2.73 2.95 3.17 V PVD2LVL[2:0]=0b110 42
调压器上电时的浪涌电流（POR 或从待机唤醒） IRUSH 100 150 mA 42
NRST 复位最低宽度 TNRST 10 µs 42
PVD1 复位解除时间 TIPVD1 300 380 460 µs 42
NRST 复位解除时间 TINRST 25 35 50 µs 42
上电复位解除时间 TRSTPOR 2500 3000 µs 43
运行模式电流（全模块时钟 OFF） ICC_RUN 33 mA while(1), 全模块时钟 OFF, fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V 44
运行模式电流（全模块时钟 ON） ICC_RUN 48 mA while(1), 全模块时钟 ON, fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V 44
休眠模式电流（全模块时钟 OFF） ICC_SLEEP 24 mA 全模块时钟 OFF, fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V 44
休眠模式电流（全模块时钟 ON） ICC_SLEEP 39 mA 全模块时钟 ON, fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V 44
运行模式电流（全模块时钟 OFF，超低速） ICC_RUN 8 mA while(1), 全模块时钟 OFF, fHCLK=8MHz, TA=105°C, VCC=1.8~3.6V 45
停止模式电流 ICC_STP 6.5 mA PWC_PWRC1.STPDAS=0b00, TA=105°C, VCC=1.8~3.6V 46
掉电模式 1 电流 ICC_PD 31 µA 掉电模式 1, TA=105°C, VCC=1.8~3.6V 47
供电电流（读模式） IVCC 5 mA 读模式, VCC=1.8~3.6V 52
供电电流（编程模式） IVCC 10 mA 编程模式, VCC=1.8~3.6V 52
编程，块擦除次数 Nend 10 千次 TA=85℃ 53
静电放电电压（人体模型） VESD(HBM) 4000 V TA=+25°C, ANSI/ESDA/JEDEC JS-001 53
静电放电电压（充电设备模型） VESD(CDM) 1000 V TA=+25°C, ANSI/ESDA/JEDEC JS-002 53
静态 Latch-up LU 200 mA TA=+105°C, JESD78A 53
I/O 输入泄露电流 ILKG 1 µA VSS≤VIN≤VCC 54
I/O 输入泄露电流 ILKG 10 µA VIN=5.5V 54
弱上拉等效电阻 RPU 10 30 150 kΩ VIN=VSS, 1.8≤VCC≤3.6V 54
弱下拉等效电阻 RPD 5 20 50 kΩ VIN=VCC, 1.8≤VCC≤3.6V 54
HRC 振荡器频率精度 fHRC -2 2 % TA=-40~105℃ 51
MRC 振荡器频率 fMRC 7.2 8 8.8 MHz 51
LRC 振荡器频率 fLRC 27.853 32.768 37.683 kHz 51
SWDTLRC 振荡器频率 fSWDTLRC 9 10 11 kHz 51
XTAL 精度 AXTAL -500 500 ppm 49

CAD (KiCad official)

  • Symbol: HC32F448JATI-LQ48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hc32f448jati-lq48-etched.step / hc32f448jati-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f448jati-lq48.step / hc32f448jati-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (94 pp, sha256 69113ad72760a1d2, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF