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HC32F420JATB-LQ48

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HC32F420JATB-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F420JATB-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD03 bidirectional GPIO PD03 with alternate functions ATIM0_BK, CTIM0_CH0, CTIM1_TOGP, ATIM3_BK and USART2_TXD; port resets to analog input state.
2 PC13 bidirectional GPIO PC13 that doubles as LVD voltage-detect input LVDIN0, with alternate functions SPI0_SCK, CTIM2_CH0, I2C1_SCL, ATIM3_CH0A and USART3_NCTS.
3 PC14 bidirectional GPIO PC14 with alternate functions SPI0_MISO, CTIM2_CH1, I2C1_SDA, ATIM3_CH1A and USART3_NRTS.
4 PC15 bidirectional GPIO PC15 with alternate functions SPI0_MOSI, CTIM2_ETR, ATIM3_CH2A and USART3_SCK.
5 PD00 bidirectional GPIO PD00 shared with the XTH oscillator input XTHI (8-32 MHz crystal/resonator), with alternate functions SPI0_CS, CTIM0_CH2, I2C0_SCL, ATIM3_CH0B and I2C1_SCL.
6 PD01 bidirectional GPIO PD01 shared with the XTH oscillator output XTHO, with alternate functions LVD_OUT, CTIM0_CH3, I2C0_SDA, ATIM3_CH2B and I2C1_SDA.
7 NRESET input Active-low reset input (CMOS, 200 mV Schmitt hysteresis) with a non-disconnectable weak pull-up of about 80 kΩ; VIH min 0.8·VCC, VIL max 0.8 V.
8 AVSS power_in Analog ground for the ADC, voltage comparator and analog circuits; ground-pin difference to VSS must not exceed 50 mV.
9 AVCC power_in Analog supply, 2.0-5.5 V, must be the same as DVCC (at most 300 mV difference during power-up and operation).
10 PA00 bidirectional GPIO PA00 with analog input AIN0/VCIN0, alternate functions ATIM0_ETR, CTIM0_CH0, CTIM0_ETR, VC0_OUT and USART1_NCTS.
11 PA01 bidirectional GPIO PA01 with analog input AIN1/VCIN1, alternate functions MCO, CTIM0_CH1, SPI1_CS, USART2_NCTS and USART1_NRTS.
12 PA02 bidirectional GPIO PA02 with analog input AIN2/VCIN2, alternate functions CTIM1_TOGN, CTIM0_CH2, VC1_OUT, USART3_NRTS and USART1_TXD.
13 PA03 bidirectional GPIO PA03 with analog input AIN3/VCIN3, alternate functions LVD_OUT, CTIM0_CH3, SPI1_SCK, USART3_TXD and USART1_RXD.
14 PA04 bidirectional GPIO PA04 with analog input AIN4/VCIN4, alternate functions ATIM3_CH0A, PCLK0_OUT, SPI0_CS, USART3_RXD and USART1_SCK.
15 PA05 bidirectional GPIO PA05 with analog input AIN5/VCIN5, alternate functions ATIM3_CH1A, CTIM0_CH0, CTIM0_ETR, USART3_NCTS and SPI0_SCK.
16 PA06 bidirectional GPIO PA06 with analog input AIN6, alternate functions ATIM3_CH2A, USART2_RXD, CTIM1_CH0, ATIM3_BK and SPI0_MISO.
17 PA07 bidirectional GPIO PA07 with analog input AIN7, alternate functions ATIM3_CH0B, USART3_TXD, CTIM1_CH1, USART2_NRTS and SPI0_MOSI.
18 PB00 bidirectional GPIO PB00 with analog input AIN8/VCIN6, alternate functions ATIM3_CH1B, CTIM2_ETR, CTIM1_CH2, ATIM0_CH0A and USART3_SCK.
19 PB01 bidirectional GPIO PB01 with analog input AIN9/ExRef/VCIN7 (ExRef is the external ADC reference), alternate functions ATIM3_CH2B, CTIM2_TOGP, CTIM1_CH3, ATIM0_CH0B and PCLK1_OUT.
20 PB02 bidirectional GPIO PB02 with alternate functions CTIM0_CH3, CTIM2_TOGN, ATIM3_GATE, ATIM0_GATE and USART2_RXD.
21 PB10 bidirectional GPIO PB10 with alternate functions CTIM0_CH2, I2C1_SCL and USART2_TXD.
22 VCAP power_out Output of the internal LDO that supplies the core; for internal circuit use only and requires an external decoupling capacitor as given in the power supply scheme (Section 6.1.3).
23 DVSS power_in Digital ground; ground-pin difference to VSS must not exceed 50 mV.
24 DVCC power_in Digital supply, 2.0-5.5 V standard operating voltage, must match AVCC within 300 mV.
25 PB12 bidirectional GPIO PB12 with analog input VCIN8, alternate functions I2C0_SCL, ATIM3_BK, CTRIM_ETRTOG, SPI1_CS and USART2_SCK.
26 PB13 bidirectional GPIO PB13 with alternate functions I2C0_SDA, ATIM3_CH0B, SPI1_SCK and USART2_NCTS.
27 PB14 bidirectional GPIO PB14 with alternate functions ATIM3_CH1B, CTIM1_TOGP, SPI1_MISO and USART2_NRTS.
28 PB15 bidirectional GPIO PB15 with alternate functions MCO, ATIM3_CH2B, CTIM1_TOGN and SPI1_MOSI.
29 PA08 bidirectional GPIO PA08 with alternate functions CTIM0_TOGP, ATIM3_CH0A, CTRIM_ETRTOG, USART3_RXD and USART0_SCK.
30 PA09 bidirectional GPIO PA09 with alternate functions CTIM0_TOGN, ATIM3_CH1A, ATIM0_BK, CTIM1_CH2 and USART0_TXD.
31 PA10 bidirectional GPIO PA10 with alternate functions I2C1_SCL, ATIM3_CH2A, ATIM0_CH0A, CTIM1_CH3 and USART0_RXD.
32 PA11 bidirectional GPIO PA11 with alternate functions VC0_OUT, ATIM3_GATE, ATIM0_CH0B, USART1_NCTS and USART0_NCTS.
33 PA12 bidirectional GPIO PA12 with alternate functions VC1_OUT, ATIM3_ETR, ATIM0_GATE, USART1_NRTS and USART0_NRTS.
34 PA13 bidirectional GPIO PA13 with alternate functions ATIM3_BK, CTIM2_CH2, ATIM0_ETR, USART1_RXD and I2C0_SCL.
35 DVSS power_in Digital ground; ground-pin difference to VSS must not exceed 50 mV.
36 DVCC power_in Digital supply, 2.0-5.5 V standard operating voltage, must match AVCC within 300 mV.
37 PA14 bidirectional GPIO PA14 with alternate functions CTIM0_CH1, CTIM2_CH3, USART2_SCK, USART1_TXD and I2C0_SDA.
38 PA15 bidirectional GPIO PA15 with alternate functions SPI0_CS, CTIM1_CH0, CTIM1_ETR, USART1_SCK and USART0_TXD.
39 PB03 bidirectional GPIO PB03 with alternate functions CTIM0_CH1, USART0_RXD, I2C1_SDA, ATIM3_CH1B and SPI0_SCK.
40 PB04 bidirectional GPIO PB04 with analog input VCIN9, alternate functions CTIM1_CH0, CTIM2_TOGP, PCLK0_OUT, ATIM3_CH2B and SPI0_MISO.
41 PB05 bidirectional GPIO PB05 with analog input VCIN10, alternate functions CTIM1_CH1, CTIM2_TOGN, USART3_SCK, USART2_TXD and SPI0_MOSI.
42 PB06 bidirectional GPIO PB06 with alternate functions USART0_TXD, CTIM2_CH0, SPI1_MISO, I2C0_SCL and USART2_RXD.
43 PB07 bidirectional GPIO PB07 that doubles as LVD voltage-detect input LVDIN1, with alternate functions USART0_RXD, CTIM2_CH1, SPI1_MOSI, I2C0_SDA and PCLK1_OUT.
44 PB11/BOOT0 bidirectional Pin shared by GPIO PB11 and BOOT0; during power-up, external RESET and LVD reset, BOOT0 high enters ISP (online programming) mode and BOOT0 low selects normal operation.
45 PB08 bidirectional GPIO PB08 that doubles as LVD voltage-detect input LVDIN2, with alternate functions CTRIM_ETRTOG, CTIM2_CH2, I2C0_SCL and ATIM0_BK.
46 PB09 bidirectional GPIO PB09 with alternate functions SPI1_CS, CTIM2_CH3, I2C0_SDA and I2C1_SDA.
47 DVSS power_in Digital ground; ground-pin difference to VSS must not exceed 50 mV.
48 DVCC power_in Digital supply, 2.0-5.5 V standard operating voltage, must match AVCC within 300 mV.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
外部输入电压范围 Vex 0 V 35
检测阈值 Vlevel 1.7 1.8 1.9 V LVD_CR.VTDS = 0b0000 35
检测阈值 Vlevel 1.8 1.9 2 V LVD_CR.VTDS = 0b0001 35
检测阈值 Vlevel 1.89 2 2.11 V LVD_CR.VTDS = 0b0010 35
检测阈值 Vlevel 1.98 2.1 2.22 V LVD_CR.VTDS = 0b0011 35
检测阈值 Vlevel 2.08 2.2 2.32 V LVD_CR.VTDS = 0b0100 35
检测阈值 Vlevel 2.17 2.3 2.43 V LVD_CR.VTDS = 0b0101 35
检测阈值 Vlevel 2.27 2.4 2.53 V LVD_CR.VTDS = 0b0110 35
检测阈值 Vlevel 2.36 2.5 2.64 V LVD_CR.VTDS = 0b0111 35
检测阈值 Vlevel 2.46 2.6 2.74 V LVD_CR.VTDS = 0b1000 35
检测阈值 Vlevel 2.55 2.7 2.85 V LVD_CR.VTDS = 0b1001 35
检测阈值 Vlevel 2.65 2.8 2.95 V LVD_CR.VTDS = 0b1010 35
检测阈值 Vlevel 2.74 2.9 3.06 V LVD_CR.VTDS = 0b1011 35
检测阈值 Vlevel 2.84 3 3.17 V LVD_CR.VTDS = 0b1100 35
检测阈值 Vlevel 2.93 3.1 3.27 V LVD_CR.VTDS = 0b1101 35
检测阈值 Vlevel 3.02 3.2 3.38 V LVD_CR.VTDS = 0b1110 35
检测阈值 Vlevel 3.12 3.3 3.48 V LVD_CR.VTDS = 0b1111 35
Internal 2.5v Reference Voltage VREF25 2.475 2.5 2.525 V 常温 25°C VCC=3.3V 35
Internal 2.5v Reference Voltage VREF25 2.463 2.5 2.538 V -40 ~ 105°C VCC=2.8V~5.5V 35
Internal 1.5v Reference Voltage VREF15 1.485 1.5 1.515 V 常温 25°C VCC=3.3V 35
Internal 1.5v Reference Voltage VREF15 1.477 1.5 1.523 V -40 ~ 105°C VCC=2.0V~5.5V 35
响应时间 Tresponse 80 μs 35
建立时间 Tsetup 400 μs 35
迟滞电压 Vhyste 40 mV 35
滤波时间 Tfilter 7 μs LVD_CR.FltTime = 0b000 35
滤波时间 Tfilter 20 μs LVD_CR.FltTime = 0b001 35
滤波时间 Tfilter 47 μs LVD_CR.FltTime = 0b010 35
滤波时间 Tfilter 100 μs LVD_CR.FltTime = 0b011 35
滤波时间 Tfilter 420 μs LVD_CR.FltTime = 0b100 35
滤波时间 Tfilter 1700 μs LVD_CR.FltTime = 0b101 35
滤波时间 Tfilter 6820 μs LVD_CR.FltTime = 0b110 35
滤波时间 Tfilter 27300 μs LVD_CR.FltTime = 0b111 35
Internal 2.5v 1.5v temperature coefficient TCoeff 120 ppm/°C -40 ~ 105°C 35
BGR stable time Tstable 20 μs 常温 25°C VCC=3.3V 35
POR 释放电压（上电过程） VPOR 1.65 V 34
PDR 检测电压（掉电过程） VPDR 1.5 V 34

CAD (KiCad official)

  • Symbol: HC32F420JATB-LQ48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hc32f420jatb-lq48-etched.step / hc32f420jatb-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f420jatb-lq48.step / hc32f420jatb-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (66 pp, sha256 c5ceedab630019d8, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF