component
HC32F334K8TI-LQFP64
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HC32F334K8TI-LQFP64
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
HC32F334K8TI-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | GPIO PF2 with EIRQ2, USART1_CK/USART4_CK, TMR6_TRIGB and TMR4_ADSM alternate functions; 5 V tolerant, input must not exceed 5 V and internal pull-up/down is disabled when input is above VCC. |
| 2 | PC13 | bidirectional | GPIO PC13 with EIRQ13/WKUP3_1 wake-up, RTC_OUT and TMR4 PWM alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 3 | PC14/XTAL32_IN | input | 32.768 kHz low-speed oscillator input XTAL32_IN, shared with GPIO PC14 and EIRQ14; load capacitors per the XTAL32 application circuit (section 3.3.6.3). |
| 4 | PC15/XTAL32_OUT | output | 32.768 kHz low-speed oscillator output XTAL32_OUT, shared with GPIO PC15 and EIRQ15; load capacitors per the XTAL32 application circuit (section 3.3.6.3). |
| 5 | PF0/XTAL_IN | input | External high-speed oscillator input XTAL_IN for a 4-25 MHz crystal or resonator (Table 3-16), shared with GPIO PF0 and EIRQ0. |
| 6 | PF1/XTAL_OUT | output | External high-speed oscillator output XTAL_OUT for a 4-25 MHz crystal or resonator (Table 3-16), shared with GPIO PF1 and EIRQ1. |
| 7 | NRST | input | Active-low reset input; if unused, connect a pull-up resistor to VCC (section 2.4). |
| 8 | PC0 | bidirectional | GPIO PC0 with ADC12_IN10 analog input, EIRQ0 and SPI_NSS3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 9 | PC1 | bidirectional | GPIO PC1 with ADC12_IN11 analog input, EIRQ1, CMP3_OUT and SPI_NSS2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 10 | PC2 | bidirectional | GPIO PC2 with ADC12_IN12 analog input, EIRQ2 and SPI_NSS1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 11 | PC3 | bidirectional | GPIO PC3 with ADC12_IN13 analog input, EIRQ3 and EMB_PORT1_IN2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 12 | AVSS/VREFL | power_in | Analog ground and low reference voltage (VREFL); tie to VSS when the analog modules are not used (section 2.4). |
| 13 | AVCC/VREFH | power_in | Analog supply and high reference voltage (VREFH), same voltage as VCC (1.8-3.63 V); tie to VCC when the analog modules are not used. |
| 14 | PA0 | bidirectional | GPIO PA0 with ADC1_IN0 analog input, EIRQ0/WKUP0_0, CMP1_OUT and FCMREF alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 15 | PA1 | bidirectional | GPIO PA1 with ADC1_IN1 analog input, RTC_CLK1, EIRQ1 and EMB_PORT1_IN4 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 16 | PA2 | bidirectional | GPIO PA2 with ADC1_IN2 analog input, CMP1_INM2, EIRQ2 and ADTRG1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 17 | PA3 | bidirectional | GPIO PA3 with ADC1_IN3 analog input, CMP1/2/3 positive inputs (INP2), EIRQ3 and ADTRG2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 18 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 19 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 20 | PA4 | bidirectional | GPIO PA4 with ADC12_IN4, DAC1_OUT1, CMP1/2/3 negative inputs (INM1), EIRQ4, USART1_CK and USART2_CK alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 21 | PA5 | bidirectional | GPIO PA5 with ADC12_IN5, DAC1_OUT2 and EIRQ5 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 22 | PA6 | bidirectional | GPIO PA6 with ADC123_IN6, DAC2_OUT1, EIRQ6 and CMP1_OUT alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 23 | PA7 | bidirectional | GPIO PA7 with ADC123_IN7, CMP1_INP1, EIRQ7 and ADTRG3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 24 | PC4 | bidirectional | GPIO PC4 with ADC12_IN14 analog input and EIRQ4 alternate function; analog input voltage must not exceed VREFH/AVCC. |
| 25 | PC5 | bidirectional | GPIO PC5 with ADC12_IN15 analog input, EIRQ5 and EMB_PORT1_IN3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 26 | PB0 | bidirectional | GPIO PB0 with ADC123_IN8 analog input, CMP2_INP1, EIRQ0 and ADTRG1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 27 | PB1 | bidirectional | GPIO PB1 with ADC123_IN9 analog input, EIRQ1/WKUP0_1, ADTRG2 and MCO_1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 28 | PB2 | bidirectional | GPIO PB2 with ADC3_IN10 analog input, CMP2_INM2, EIRQ2/WKUP0_2, ADTRG3 and MCO_2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 29 | PB10 | bidirectional | GPIO PB10 with ADC3_IN11 analog input, EIRQ10 and HRPWM_EEV9 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 30 | PB11 | bidirectional | GPIO PB11 with CMP3_INP1, EIRQ11 and HRPWM_EEV7 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 31 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 32 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 33 | PB12 | bidirectional | GPIO PB12 with ADC3_IN0 analog input, EIRQ12, HRPWM_4_PWMA, USART1_CK and USART3_CK alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 34 | PB13 | bidirectional | GPIO PB13 with ADC3_IN1 analog input, EIRQ13 and HRPWM_4_PWMB alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 35 | PB14 | bidirectional | GPIO PB14 with ADC3_IN2 analog input, EIRQ14 and HRPWM_5_PWMA alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 36 | PB15 | bidirectional | GPIO PB15 with ADC3_IN3 analog input, CMP3_INM2, RTC_CLK2, EIRQ15 and HRPWM_5_PWMB alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 37 | PC6 | bidirectional | GPIO PC6 with EIRQ6, HRPWM_1_PWMA, CMP3_OUT and HRPWM_EEV10 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 38 | PC7 | bidirectional | GPIO PC7 with EIRQ7, HRPWM_1_PWMB and EMB_PORT1_IN5 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 39 | PC8 | bidirectional | GPIO PC8 with EIRQ8, HRPWM_6_PWMA and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 40 | PC9 | bidirectional | GPIO PC9 with EIRQ9, HRPWM_6_PWMB and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 41 | PA8 | bidirectional | GPIO PA8 with EXVREF, EIRQ8/WKUP2_0, TRACED0, USART1_CK/USART2_CK, CTCREF and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 42 | PA9 | bidirectional | GPIO PA9 with EIRQ9, TRACECLK, EMB_PORT1_IN3 and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 43 | PA10 | bidirectional | GPIO PA10 with EIRQ10/WKUP2_2, TRACED1, CMP3_OUT and EMB_PORT1_IN5 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 44 | PA11 | bidirectional | GPIO PA11 with EIRQ11/WKUP2_3, TRACED2, CMP1_OUT and EMB_PORT1_IN2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 45 | PA12 | bidirectional | GPIO PA12 with EIRQ12/WKUP3_0, TRACED3, CMP1_OUT, CMP2_OUT, SPI_NSS1 and FCMREF alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 46 | PA13 | bidirectional | GPIO PA13 with EIRQ13, JTMS_SWDIO, CMP3_OUT and ADTRG3 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 47 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 49 | PA14 | bidirectional | GPIO PA14 with EIRQ14/WKUP3_2, JTCK_SWCLK and ADTRG2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 50 | PA15 | bidirectional | GPIO PA15 with EIRQ15/WKUP3_3, JTDI, HRPWM_EEV1 and EMB_PORT1_IN2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 51 | PC10 | bidirectional | GPIO PC10 with EIRQ10 and TMR6_1 PWM alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 52 | PC11 | bidirectional | GPIO PC11 with EIRQ11 and HRPWM_EEV2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 53 | PC12 | bidirectional | GPIO PC12 with EIRQ12, HRPWM_EEV1, USART1_CK and USART3_CK alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 54 | PD2 | bidirectional | GPIO PD2 with EIRQ2, CMP3_OUT and HRPWM_EEV10 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 55 | PB3 | bidirectional | GPIO PB3 with EIRQ3/WKUP0_3, JTDO_TRACESWO and HRPWM_SCOUT alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 56 | PB4 | bidirectional | GPIO PB4 with EIRQ4/WKUP1_0, NJTRST and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 57 | PB5 | bidirectional | GPIO PB5 with EIRQ5/WKUP1_1, USART1_CK/USART2_CK and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 58 | PB6 | bidirectional | GPIO PB6 (I2C-capable pin, Table 3-28) with EIRQ6/WKUP1_2, SPI_NSS2, CTCREF, CMP1_OUT and ADTRG1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 59 | PB7 | bidirectional | GPIO PB7 (I2C-capable pin, Table 3-28) with EIRQ7/WKUP1_3, FCMREF, CMP2_OUT and ADTRG2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 60 | PF3/MD | bidirectional | GPIO PF3 and MD mode input; MD must be held low when NRST is released, and a 4.7 kΩ pull-down to VSS is recommended (section 2.4). |
| 61 | PB8 | bidirectional | GPIO PB8 with PVD2EXINP (PVD2 external comparison voltage input), EIRQ8, SPI_NSS3, ADTRG1 and FCMREF alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 62 | PB9 | bidirectional | GPIO PB9 with EIRQ9/WKUP2_1, CMP1_OUT, CMP2_OUT and EMB_PORT1_IN4 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 63 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 64 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压范围 (system supply) | VCC | 1.8 | 3.63 | V | 12 | ||
| 工作温度范围 | -40 | 105 | ℃ | 12 | |||
| 数字外部事件响应时间 | TLAT(DEEV) | 60 | 70 | ns | 30pF负载 | 67 | |
| 模拟外部事件响应时间 | TLAT(AEEV) | 75 | 85 | ns | 30pF负载 | 67 | |
| 最小外部事件脉冲宽度 | TW(EEV) | 12.5 | ns | 67 | |||
| 外部事件反应jitter | TJIT (EEV) | 1 | tPCLK0 | 从HRPWM_EEVy输入到HRPWM__PWMA/B输出端口 | 67 | ||
| 同步输入信号HRPWM_TRGA~D最小脉宽 | Tw(TRGA-D) | 2 | tPCLK0 | 67 | |||
| 同步请求响应时间 | TRES(TRGA-D) | 4 | tPCLK0 | 67 | |||
| 同步输出信号HRPWM_SYNCOUT最小脉宽 | Tw(SYNCOUT) | 16 | 65535 | tPCLK0 | 67 | ||
| SCL频率 | fSCL | 0 | 100 | KHz | 标准模式（SM） | 68 | |
| SCL频率 | fSCL | 0 | 400 | KHz | 快速模式（FM） | 68 | |
| SCL频率 | fSCL | 0 | 1000 | KHz | 快速模式Plus（FM+） | 68 | |
| 开始条件/重新开始条件Hold | tHD;STA | 4 | μs | 标准模式（SM） | 68 | ||
| 开始条件/重新开始条件Hold | tHD;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| 开始条件/重新开始条件Hold | tHD;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| SCL低电平 | tLOW | 4.7 | μs | 标准模式（SM） | 68 | ||
| SCL低电平 | tLOW | 1.3 | μs | 快速模式（FM） | 68 | ||
| SCL低电平 | tLOW | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| SCL高电平 | tHIGH | 4 | μs | 标准模式（SM） | 68 | ||
| SCL高电平 | tHIGH | 0.6 | μs | 快速模式（FM） | 68 | ||
| SCL高电平 | tHIGH | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 重新开始条件Setup | tSU;STA | 4.7 | μs | 标准模式（SM） | 68 | ||
| 重新开始条件Setup | tSU;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| 重新开始条件Setup | tSU;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 数据Hold | tHD;DAT | 0 | μs | 标准模式（SM） | 68 | ||
| SCL/SDA的上升时间 | tR | 1000 | ns | 标准模式（SM） | 68 | ||
| SCL/SDA的上升时间 | tR | 300 | ns | 快速模式（FM） | 68 | ||
| SCL/SDA的上升时间 | tR | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| SCL/SDA的下降时间 | tF | 300 | ns | 标准模式（SM） | 68 | ||
| SCL/SDA的下降时间 | tF | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| 停止条件Setup | tSU;STO | 4 | μs | 标准模式（SM） | 68 | ||
| 停止条件Setup | tSU;STO | 0.6 | μs | 快速模式（FM） | 68 | ||
| 停止条件Setup | tSU;STO | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 4.7 | μs | 标准模式（SM） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 1.3 | μs | 快速模式（FM） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| 负载电容 | Cb | 400 | pF | 标准模式（SM） | 68 | ||
| 负载电容 | Cb | 550 | pF | 快速模式Plus（FM+） | 68 | ||
| Data输入建立时间（从机） | tsu(SI) | 4 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| Data输入保持时间（从机） | th(SI) | 3 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| Data输出有效时间（从机） | tv(SO) | 15 | ns | 从机模式，2.7V≤Vcc≤3.63V | 69 | ||
| Data输出有效时间（从机） | tv(SO) | 26 | ns | 从机模式，1.8V≤Vcc＜2.7V | 69 | ||
| Data输入建立时间（主机） | tsu(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| Data输入建立时间（主机） | tsu(MI) | 9 | ns | 主机模式，1.8V≤Vcc＜2.7V | 69 | ||
| Data输入保持时间（主机） | th(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| Data输入保持时间（主机） | th(MI) | 15 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 | ||
| Data输出有效时间（主机） | tv(MO) | 4 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| Data输出有效时间（主机） | tv(MO) | 9 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
CAD (KiCad official)
- Symbol:
HC32F334K8TI-LQFP64 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
hc32f334k8ti-lqfp64-etched.step/hc32f334k8ti-lqfp64-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f334k8ti-lqfp64.step/hc32f334k8ti-lqfp64.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (102 pp, sha256
bf3aa4841b430601, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HC32F334K8TI-LQFP64
**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
HC32F334K8TI-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | GPIO PF2 with EIRQ2, USART1_CK/USART4_CK, TMR6_TRIGB and TMR4_ADSM alternate functions; 5 V tolerant, input must not exceed 5 V and internal pull-up/down is disabled when input is above VCC. |
| 2 | PC13 | bidirectional | GPIO PC13 with EIRQ13/WKUP3_1 wake-up, RTC_OUT and TMR4 PWM alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 3 | PC14/XTAL32_IN | input | 32.768 kHz low-speed oscillator input XTAL32_IN, shared with GPIO PC14 and EIRQ14; load capacitors per the XTAL32 application circuit (section 3.3.6.3). |
| 4 | PC15/XTAL32_OUT | output | 32.768 kHz low-speed oscillator output XTAL32_OUT, shared with GPIO PC15 and EIRQ15; load capacitors per the XTAL32 application circuit (section 3.3.6.3). |
| 5 | PF0/XTAL_IN | input | External high-speed oscillator input XTAL_IN for a 4-25 MHz crystal or resonator (Table 3-16), shared with GPIO PF0 and EIRQ0. |
| 6 | PF1/XTAL_OUT | output | External high-speed oscillator output XTAL_OUT for a 4-25 MHz crystal or resonator (Table 3-16), shared with GPIO PF1 and EIRQ1. |
| 7 | NRST | input | Active-low reset input; if unused, connect a pull-up resistor to VCC (section 2.4). |
| 8 | PC0 | bidirectional | GPIO PC0 with ADC12_IN10 analog input, EIRQ0 and SPI_NSS3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 9 | PC1 | bidirectional | GPIO PC1 with ADC12_IN11 analog input, EIRQ1, CMP3_OUT and SPI_NSS2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 10 | PC2 | bidirectional | GPIO PC2 with ADC12_IN12 analog input, EIRQ2 and SPI_NSS1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 11 | PC3 | bidirectional | GPIO PC3 with ADC12_IN13 analog input, EIRQ3 and EMB_PORT1_IN2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 12 | AVSS/VREFL | power_in | Analog ground and low reference voltage (VREFL); tie to VSS when the analog modules are not used (section 2.4). |
| 13 | AVCC/VREFH | power_in | Analog supply and high reference voltage (VREFH), same voltage as VCC (1.8-3.63 V); tie to VCC when the analog modules are not used. |
| 14 | PA0 | bidirectional | GPIO PA0 with ADC1_IN0 analog input, EIRQ0/WKUP0_0, CMP1_OUT and FCMREF alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 15 | PA1 | bidirectional | GPIO PA1 with ADC1_IN1 analog input, RTC_CLK1, EIRQ1 and EMB_PORT1_IN4 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 16 | PA2 | bidirectional | GPIO PA2 with ADC1_IN2 analog input, CMP1_INM2, EIRQ2 and ADTRG1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 17 | PA3 | bidirectional | GPIO PA3 with ADC1_IN3 analog input, CMP1/2/3 positive inputs (INP2), EIRQ3 and ADTRG2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 18 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 19 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 20 | PA4 | bidirectional | GPIO PA4 with ADC12_IN4, DAC1_OUT1, CMP1/2/3 negative inputs (INM1), EIRQ4, USART1_CK and USART2_CK alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 21 | PA5 | bidirectional | GPIO PA5 with ADC12_IN5, DAC1_OUT2 and EIRQ5 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 22 | PA6 | bidirectional | GPIO PA6 with ADC123_IN6, DAC2_OUT1, EIRQ6 and CMP1_OUT alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 23 | PA7 | bidirectional | GPIO PA7 with ADC123_IN7, CMP1_INP1, EIRQ7 and ADTRG3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 24 | PC4 | bidirectional | GPIO PC4 with ADC12_IN14 analog input and EIRQ4 alternate function; analog input voltage must not exceed VREFH/AVCC. |
| 25 | PC5 | bidirectional | GPIO PC5 with ADC12_IN15 analog input, EIRQ5 and EMB_PORT1_IN3 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 26 | PB0 | bidirectional | GPIO PB0 with ADC123_IN8 analog input, CMP2_INP1, EIRQ0 and ADTRG1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 27 | PB1 | bidirectional | GPIO PB1 with ADC123_IN9 analog input, EIRQ1/WKUP0_1, ADTRG2 and MCO_1 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 28 | PB2 | bidirectional | GPIO PB2 with ADC3_IN10 analog input, CMP2_INM2, EIRQ2/WKUP0_2, ADTRG3 and MCO_2 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 29 | PB10 | bidirectional | GPIO PB10 with ADC3_IN11 analog input, EIRQ10 and HRPWM_EEV9 alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 30 | PB11 | bidirectional | GPIO PB11 with CMP3_INP1, EIRQ11 and HRPWM_EEV7 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 31 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 32 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 33 | PB12 | bidirectional | GPIO PB12 with ADC3_IN0 analog input, EIRQ12, HRPWM_4_PWMA, USART1_CK and USART3_CK alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 34 | PB13 | bidirectional | GPIO PB13 with ADC3_IN1 analog input, EIRQ13 and HRPWM_4_PWMB alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 35 | PB14 | bidirectional | GPIO PB14 with ADC3_IN2 analog input, EIRQ14 and HRPWM_5_PWMA alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 36 | PB15 | bidirectional | GPIO PB15 with ADC3_IN3 analog input, CMP3_INM2, RTC_CLK2, EIRQ15 and HRPWM_5_PWMB alternate functions; analog input voltage must not exceed VREFH/AVCC. |
| 37 | PC6 | bidirectional | GPIO PC6 with EIRQ6, HRPWM_1_PWMA, CMP3_OUT and HRPWM_EEV10 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 38 | PC7 | bidirectional | GPIO PC7 with EIRQ7, HRPWM_1_PWMB and EMB_PORT1_IN5 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 39 | PC8 | bidirectional | GPIO PC8 with EIRQ8, HRPWM_6_PWMA and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 40 | PC9 | bidirectional | GPIO PC9 with EIRQ9, HRPWM_6_PWMB and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 41 | PA8 | bidirectional | GPIO PA8 with EXVREF, EIRQ8/WKUP2_0, TRACED0, USART1_CK/USART2_CK, CTCREF and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 42 | PA9 | bidirectional | GPIO PA9 with EIRQ9, TRACECLK, EMB_PORT1_IN3 and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 43 | PA10 | bidirectional | GPIO PA10 with EIRQ10/WKUP2_2, TRACED1, CMP3_OUT and EMB_PORT1_IN5 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 44 | PA11 | bidirectional | GPIO PA11 with EIRQ11/WKUP2_3, TRACED2, CMP1_OUT and EMB_PORT1_IN2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 45 | PA12 | bidirectional | GPIO PA12 with EIRQ12/WKUP3_0, TRACED3, CMP1_OUT, CMP2_OUT, SPI_NSS1 and FCMREF alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 46 | PA13 | bidirectional | GPIO PA13 with EIRQ13, JTMS_SWDIO, CMP3_OUT and ADTRG3 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 47 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
| 49 | PA14 | bidirectional | GPIO PA14 with EIRQ14/WKUP3_2, JTCK_SWCLK and ADTRG2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 50 | PA15 | bidirectional | GPIO PA15 with EIRQ15/WKUP3_3, JTDI, HRPWM_EEV1 and EMB_PORT1_IN2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 51 | PC10 | bidirectional | GPIO PC10 with EIRQ10 and TMR6_1 PWM alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 52 | PC11 | bidirectional | GPIO PC11 with EIRQ11 and HRPWM_EEV2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 53 | PC12 | bidirectional | GPIO PC12 with EIRQ12, HRPWM_EEV1, USART1_CK and USART3_CK alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 54 | PD2 | bidirectional | GPIO PD2 with EIRQ2, CMP3_OUT and HRPWM_EEV10 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 55 | PB3 | bidirectional | GPIO PB3 with EIRQ3/WKUP0_3, JTDO_TRACESWO and HRPWM_SCOUT alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 56 | PB4 | bidirectional | GPIO PB4 with EIRQ4/WKUP1_0, NJTRST and MCO_2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 57 | PB5 | bidirectional | GPIO PB5 with EIRQ5/WKUP1_1, USART1_CK/USART2_CK and MCO_1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 58 | PB6 | bidirectional | GPIO PB6 (I2C-capable pin, Table 3-28) with EIRQ6/WKUP1_2, SPI_NSS2, CTCREF, CMP1_OUT and ADTRG1 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 59 | PB7 | bidirectional | GPIO PB7 (I2C-capable pin, Table 3-28) with EIRQ7/WKUP1_3, FCMREF, CMP2_OUT and ADTRG2 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 60 | PF3/MD | bidirectional | GPIO PF3 and MD mode input; MD must be held low when NRST is released, and a 4.7 kΩ pull-down to VSS is recommended (section 2.4). |
| 61 | PB8 | bidirectional | GPIO PB8 with PVD2EXINP (PVD2 external comparison voltage input), EIRQ8, SPI_NSS3, ADTRG1 and FCMREF alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 62 | PB9 | bidirectional | GPIO PB9 with EIRQ9/WKUP2_1, CMP1_OUT, CMP2_OUT and EMB_PORT1_IN4 alternate functions; 5 V tolerant, input must not exceed 5 V. |
| 63 | VSS | power_in | Ground, 0 V reference for all supplies. |
| 64 | VCC | power_in | Main supply, 1.8 V to 3.63 V; place decoupling capacitors close to the VCC/VSS pairs (section 2.4, Fig. 3-2). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压范围 (system supply) | VCC | 1.8 | | 3.63 | V | | 12 |
| 工作温度范围 | | -40 | | 105 | ℃ | | 12 |
| 数字外部事件响应时间 | TLAT(DEEV) | | 60 | 70 | ns | 30pF负载 | 67 |
| 模拟外部事件响应时间 | TLAT(AEEV) | | 75 | 85 | ns | 30pF负载 | 67 |
| 最小外部事件脉冲宽度 | TW(EEV) | 12.5 | | | ns | | 67 |
| 外部事件反应jitter | TJIT (EEV) | | | 1 | tPCLK0 | 从HRPWM_EEVy输入到HRPWM_<t>_PWMA/B输出端口 | 67 |
| 同步输入信号HRPWM_TRGA~D最小脉宽 | Tw(TRGA-D) | 2 | | | tPCLK0 | | 67 |
| 同步请求响应时间 | TRES(TRGA-D) | | | 4 | tPCLK0 | | 67 |
| 同步输出信号HRPWM_SYNCOUT最小脉宽 | Tw(SYNCOUT) | 16 | | 65535 | tPCLK0 | | 67 |
| SCL频率 | fSCL | 0 | | 100 | KHz | 标准模式（SM） | 68 |
| SCL频率 | fSCL | 0 | | 400 | KHz | 快速模式（FM） | 68 |
| SCL频率 | fSCL | 0 | | 1000 | KHz | 快速模式Plus（FM+） | 68 |
| 开始条件/重新开始条件Hold | tHD;STA | 4 | | | μs | 标准模式（SM） | 68 |
| 开始条件/重新开始条件Hold | tHD;STA | 0.6 | | | μs | 快速模式（FM） | 68 |
| 开始条件/重新开始条件Hold | tHD;STA | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| SCL低电平 | tLOW | 4.7 | | | μs | 标准模式（SM） | 68 |
| SCL低电平 | tLOW | 1.3 | | | μs | 快速模式（FM） | 68 |
| SCL低电平 | tLOW | 0.5 | | | μs | 快速模式Plus（FM+） | 68 |
| SCL高电平 | tHIGH | 4 | | | μs | 标准模式（SM） | 68 |
| SCL高电平 | tHIGH | 0.6 | | | μs | 快速模式（FM） | 68 |
| SCL高电平 | tHIGH | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| 重新开始条件Setup | tSU;STA | 4.7 | | | μs | 标准模式（SM） | 68 |
| 重新开始条件Setup | tSU;STA | 0.6 | | | μs | 快速模式（FM） | 68 |
| 重新开始条件Setup | tSU;STA | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| 数据Hold | tHD;DAT | 0 | | | μs | 标准模式（SM） | 68 |
| SCL/SDA的上升时间 | tR | | | 1000 | ns | 标准模式（SM） | 68 |
| SCL/SDA的上升时间 | tR | | | 300 | ns | 快速模式（FM） | 68 |
| SCL/SDA的上升时间 | tR | | | 120 | ns | 快速模式Plus（FM+） | 68 |
| SCL/SDA的下降时间 | tF | | | 300 | ns | 标准模式（SM） | 68 |
| SCL/SDA的下降时间 | tF | | | 120 | ns | 快速模式Plus（FM+） | 68 |
| 停止条件Setup | tSU;STO | 4 | | | μs | 标准模式（SM） | 68 |
| 停止条件Setup | tSU;STO | 0.6 | | | μs | 快速模式（FM） | 68 |
| 停止条件Setup | tSU;STO | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 4.7 | | | μs | 标准模式（SM） | 68 |
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 1.3 | | | μs | 快速模式（FM） | 68 |
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 0.5 | | | μs | 快速模式Plus（FM+） | 68 |
| 负载电容 | Cb | | | 400 | pF | 标准模式（SM） | 68 |
| 负载电容 | Cb | | | 550 | pF | 快速模式Plus（FM+） | 68 |
| Data输入建立时间（从机） | tsu(SI) | 4 | | | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 |
| Data输入保持时间（从机） | th(SI) | 3 | | | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 |
| Data输出有效时间（从机） | tv(SO) | | | 15 | ns | 从机模式，2.7V≤Vcc≤3.63V | 69 |
| Data输出有效时间（从机） | tv(SO) | | | 26 | ns | 从机模式，1.8V≤Vcc＜2.7V | 69 |
| Data输入建立时间（主机） | tsu(MI) | 5 | | | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| Data输入建立时间（主机） | tsu(MI) | 9 | | | ns | 主机模式，1.8V≤Vcc＜2.7V | 69 |
| Data输入保持时间（主机） | th(MI) | 5 | | | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| Data输入保持时间（主机） | th(MI) | 15 | | | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
| Data输出有效时间（主机） | tv(MO) | | | 4 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| Data输出有效时间（主机） | tv(MO) | | | 9 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
## CAD (KiCad official)
- Symbol: `HC32F334K8TI-LQFP64`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `hc32f334k8ti-lqfp64-etched.step` / `hc32f334k8ti-lqfp64-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f334k8ti-lqfp64.step` / `hc32f334k8ti-lqfp64.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603406209819299840) (102 pp, sha256 `bf3aa4841b430601`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hc32f334k8ti-lqfp64-datasheet.pdf)