HC32F334JATI-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F334JATI-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PF2	bidirectional	General-purpose I/O PF2 (also EIRQ2 external interrupt); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
2	PC13	bidirectional	General-purpose I/O PC13 (also EIRQ13 and WKUP3_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
3	PC14/XTAL32_IN	input	32.768 kHz external low-speed oscillator input (XTAL32_IN) for a crystal or ceramic resonator, with load capacitors placed close to the pin; also usable as GPIO PC14 and EIRQ14.
4	PC15/XTAL32_OUT	output	32.768 kHz external low-speed oscillator output (XTAL32_OUT); also usable as GPIO PC15 and EIRQ15.
5	PF0/XTAL_IN	input	External high-speed oscillator input (XTAL_IN) for a 4-25 MHz crystal or ceramic resonator; also usable as GPIO PF0 and EIRQ0.
6	PF1/XTAL_OUT	output	External high-speed oscillator output (XTAL_OUT) for a 4-25 MHz crystal or ceramic resonator; also usable as GPIO PF1 and EIRQ1.
7	NRST	input	Active-low reset input; if unused, connect a resistor to VCC (pull-up), and the reset low pulse must be at least 10 µs.
8	AVSS/VREFL	power_in	Analog ground and low-side analog reference voltage (VREFL) for the analog modules; tie to VSS if the analog modules are not used.
9	AVCC/VREFH	power_in	Analog supply and high-side analog reference voltage (VREFH), at the same voltage as VCC (1.8-3.63 V); tie to VCC if the analog modules are not used.
10	PA0	bidirectional	General-purpose I/O PA0 (also ADC1_IN0, EIRQ0 and WKUP0_0); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
11	PA1	bidirectional	General-purpose I/O PA1 (also ADC1_IN1 and EIRQ1); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
12	PA2	bidirectional	General-purpose I/O PA2 (also ADC1_IN2, CMP1_INM2 and EIRQ2); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
13	PA3	bidirectional	General-purpose I/O PA3 (also ADC1_IN3, CMP1_INP2, CMP2_INP2, CMP3_INP2 and EIRQ3); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
14	PA4	bidirectional	General-purpose I/O PA4 (also ADC12_IN4, DAC1_OUT1, CMP inputs and EIRQ4); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
15	PA5	bidirectional	General-purpose I/O PA5 (also ADC12_IN5, DAC1_OUT2 and EIRQ5); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
16	PA6	bidirectional	General-purpose I/O PA6 (also ADC123_IN6, DAC2_OUT1 and EIRQ6); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
17	PA7	bidirectional	General-purpose I/O PA7 (also ADC123_IN7, CMP1_INP1 and EIRQ7); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
18	PB0	bidirectional	General-purpose I/O PB0 (also ADC123_IN8, CMP2_INP1 and EIRQ0); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
19	PB1	bidirectional	General-purpose I/O PB1 (also ADC123_IN9, EIRQ1 and WKUP0_1); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
20	PB2	bidirectional	General-purpose I/O PB2 (also ADC3_IN10, CMP2_INM2, EIRQ2 and WKUP0_2); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
21	PB10	bidirectional	General-purpose I/O PB10 (also ADC3_IN11 and EIRQ10); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
22	PB11	bidirectional	General-purpose I/O PB11 (also CMP3_INP1 and EIRQ11); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
23	VSS	power_in	Ground reference, 0 V.
24	VCC	power_in	Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme.
25	PB12	bidirectional	General-purpose I/O PB12 (also ADC3_IN0 and EIRQ12); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
26	PB13	bidirectional	General-purpose I/O PB13 (also ADC3_IN1 and EIRQ13); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
27	PB14	bidirectional	General-purpose I/O PB14 (also ADC3_IN2 and EIRQ14); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
28	PB15	bidirectional	General-purpose I/O PB15 (also ADC3_IN3, CMP3_INM2, RTC_CLK2 and EIRQ15); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH.
29	PA8	bidirectional	General-purpose I/O PA8 (also EXVREF, EIRQ8, WKUP2_0 and TRACED0); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
30	PA9	bidirectional	General-purpose I/O PA9 (also EIRQ9 and TRACECLK); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
31	PA10	bidirectional	General-purpose I/O PA10 (also EIRQ10, WKUP2_2 and TRACED1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
32	PA11	bidirectional	General-purpose I/O PA11 (also EIRQ11, WKUP2_3 and TRACED2); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
33	PA12	bidirectional	General-purpose I/O PA12 (also EIRQ12, WKUP3_0, TRACED3 and SPI_NSS1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
34	PA13	bidirectional	General-purpose I/O PA13 (also EIRQ13 and JTMS_SWDIO debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
35	VSS	power_in	Ground reference, 0 V.
36	VCC	power_in	Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme.
37	PA14	bidirectional	General-purpose I/O PA14 (also EIRQ14, WKUP3_2 and JTCK_SWCLK debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
38	PA15	bidirectional	General-purpose I/O PA15 (also EIRQ15, WKUP3_3 and JTDI debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
39	PB3	bidirectional	General-purpose I/O PB3 (also EIRQ3, WKUP0_3 and JTDO_TRACESWO debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
40	PB4	bidirectional	General-purpose I/O PB4 (also EIRQ4, WKUP1_0 and NJTRST debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
41	PB5	bidirectional	General-purpose I/O PB5 (also EIRQ5 and WKUP1_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
42	PB6	bidirectional	General-purpose I/O PB6 (also EIRQ6 and WKUP1_2; I2C-capable pin); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
43	PB7	bidirectional	General-purpose I/O PB7 (also EIRQ7 and WKUP1_3; I2C-capable pin); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
44	PF3/MD	input	Mode input MD: must be held low when NRST is released, and a 4.7 kΩ pull-down to VSS is recommended; also usable as GPIO PF3.
45	PB8	bidirectional	General-purpose I/O PB8 (also EIRQ8 and PVD2EXINP external PVD2 comparison input); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
46	PB9	bidirectional	General-purpose I/O PB9 (also EIRQ9 and WKUP2_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC.
47	VSS	power_in	Ground reference, 0 V.
48	VCC	power_in	Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme.

Key specifications

Parameter	Value
Manufacturer	XHSC
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	1.8		3.63	V		12
Operating temperature range		-40		105	℃		12
SCL frequency	fSCL	0		100	KHz	Standard mode (SM)	68
SCL frequency	fSCL	0		400	KHz	Fast mode (FM)	68
SCL frequency	fSCL	0		1000	KHz	Fast mode plus (FM+)	68
Load capacitance per bus line	Cb			400	pF	Standard mode (SM)	68
Load capacitance per bus line	Cb			550	pF	Fast mode plus (FM+)	68
SCL/SDA rise time	tR			1000	ns	Standard mode (SM)	68
SCL/SDA rise time	tR			300	ns	Fast mode (FM)	68
SCL/SDA rise time	tR			120	ns	Fast mode plus (FM+)	68
SCL/SDA fall time	tF			300	ns	Standard mode (SM)	68
SCL/SDA fall time	tF			120	ns	Fast mode plus (FM+)	68
START/RESTART condition hold time	tHD;STA	4			μs	Standard mode (SM)	68
START/RESTART condition hold time	tHD;STA	0.6			μs	Fast mode (FM)	68
START/RESTART condition hold time	tHD;STA	0.26			μs	Fast mode plus (FM+)	68
SCL low period	tLOW	4.7			μs	Standard mode (SM)	68
SCL low period	tLOW	1.3			μs	Fast mode (FM)	68
SCL low period	tLOW	0.5			μs	Fast mode plus (FM+)	68
SCL high period	tHIGH	4			μs	Standard mode (SM)	68
SCL high period	tHIGH	0.6			μs	Fast mode (FM)	68
SCL high period	tHIGH	0.26			μs	Fast mode plus (FM+)	68
Repeated START condition setup time	tSU;STA	4.7			μs	Standard mode (SM)	68
Repeated START condition setup time	tSU;STA	0.6			μs	Fast mode (FM)	68
Repeated START condition setup time	tSU;STA	0.26			μs	Fast mode plus (FM+)	68
Data hold time	tHD;DAT	0			μs	Standard mode (SM)	68
STOP condition setup time	tSU;STO	4			μs	Standard mode (SM)	68
STOP condition setup time	tSU;STO	0.6			μs	Fast mode (FM)	68
STOP condition setup time	tSU;STO	0.26			μs	Fast mode plus (FM+)	68
Bus free time between STOP and START	tBUF	4.7			μs	Standard mode (SM)	68
Bus free time between STOP and START	tBUF	1.3			μs	Fast mode (FM)	68
Bus free time between STOP and START	tBUF	0.5			μs	Fast mode plus (FM+)	68
Slave data input setup time	tsu(SI)	4			ns	Slave mode, 1.8V≤Vcc≤3.63V	69
Slave data input hold time	th(SI)	3			ns	Slave mode, 1.8V≤Vcc≤3.63V	69
Slave data output valid time	tv(SO)			15	ns	Slave mode, 2.7V≤Vcc≤3.63V	69
Slave data output valid time	tv(SO)			26	ns	Slave mode, 1.8V≤Vcc<2.7V	69
Master data input setup time	tsu(MI)	5			ns	Master mode, 2.7V≤Vcc≤3.63V	69
Master data input setup time	tsu(MI)	9			ns	Master mode, 1.8V≤Vcc<2.7V	69
Master data input hold time	th(MI)	5			ns	Master mode, 2.7V≤Vcc≤3.63V	69
Master data input hold time	th(MI)	15			ns	Master mode, 1.8V≤Vcc≤2.7V	69
Master data output valid time	tv(MO)			4	ns	Master mode, 2.7V≤Vcc≤3.63V	69
Master data output valid time	tv(MO)			9	ns	Master mode, 1.8V≤Vcc≤2.7V	69
Digital external event response time	TLAT(DEEV)		60	70	ns	Synchronous mode; from HRPWMEEVy input to HRPWM__PWMA/B output, 30pF load	67
Minimum external event pulse width	TW(EEV)	12.5			ns	Synchronous mode	67
Analog external event response time	TLAT(AEEV)		75	85	ns	Synchronous mode; from CMPy_INPz input to HRPWM__PWMA/B output, 30pF load	67
External event response jitter	TJIT(EEV)			1	tPCLK0	Synchronous mode; from HRPWM_EEVy input to HRPWM__PWMA/B output	67
Synchronous input HRPWM_TRGA~D minimum pulse width	Tw(TRGA-D)	2			tPCLK0		67
Synchronous request response time	TRES(TRGA-D)			4	tPCLK0		67
Synchronous output HRPWM_SYNCOUT minimum pulse width	Tw(SYNCOUT)	16		65535	tPCLK0		67

CAD (KiCad official)

Symbol: HC32F334JATI-LQ48
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: hc32f334jati-lq48-etched.step / hc32f334jati-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f334jati-lq48.step / hc32f334jati-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XHSC datasheet (102 pp, sha256 bf3aa4841b430601, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# HC32F334JATI-LQ48

**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32F334JATI-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | General-purpose I/O PF2 (also EIRQ2 external interrupt); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 2 | PC13 | bidirectional | General-purpose I/O PC13 (also EIRQ13 and WKUP3_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 3 | PC14/XTAL32_IN | input | 32.768 kHz external low-speed oscillator input (XTAL32_IN) for a crystal or ceramic resonator, with load capacitors placed close to the pin; also usable as GPIO PC14 and EIRQ14. |
| 4 | PC15/XTAL32_OUT | output | 32.768 kHz external low-speed oscillator output (XTAL32_OUT); also usable as GPIO PC15 and EIRQ15. |
| 5 | PF0/XTAL_IN | input | External high-speed oscillator input (XTAL_IN) for a 4-25 MHz crystal or ceramic resonator; also usable as GPIO PF0 and EIRQ0. |
| 6 | PF1/XTAL_OUT | output | External high-speed oscillator output (XTAL_OUT) for a 4-25 MHz crystal or ceramic resonator; also usable as GPIO PF1 and EIRQ1. |
| 7 | NRST | input | Active-low reset input; if unused, connect a resistor to VCC (pull-up), and the reset low pulse must be at least 10 µs. |
| 8 | AVSS/VREFL | power_in | Analog ground and low-side analog reference voltage (VREFL) for the analog modules; tie to VSS if the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply and high-side analog reference voltage (VREFH), at the same voltage as VCC (1.8-3.63 V); tie to VCC if the analog modules are not used. |
| 10 | PA0 | bidirectional | General-purpose I/O PA0 (also ADC1_IN0, EIRQ0 and WKUP0_0); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 11 | PA1 | bidirectional | General-purpose I/O PA1 (also ADC1_IN1 and EIRQ1); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 12 | PA2 | bidirectional | General-purpose I/O PA2 (also ADC1_IN2, CMP1_INM2 and EIRQ2); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 13 | PA3 | bidirectional | General-purpose I/O PA3 (also ADC1_IN3, CMP1_INP2, CMP2_INP2, CMP3_INP2 and EIRQ3); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 14 | PA4 | bidirectional | General-purpose I/O PA4 (also ADC12_IN4, DAC1_OUT1, CMP inputs and EIRQ4); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 15 | PA5 | bidirectional | General-purpose I/O PA5 (also ADC12_IN5, DAC1_OUT2 and EIRQ5); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 16 | PA6 | bidirectional | General-purpose I/O PA6 (also ADC123_IN6, DAC2_OUT1 and EIRQ6); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 17 | PA7 | bidirectional | General-purpose I/O PA7 (also ADC123_IN7, CMP1_INP1 and EIRQ7); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 18 | PB0 | bidirectional | General-purpose I/O PB0 (also ADC123_IN8, CMP2_INP1 and EIRQ0); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 19 | PB1 | bidirectional | General-purpose I/O PB1 (also ADC123_IN9, EIRQ1 and WKUP0_1); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 20 | PB2 | bidirectional | General-purpose I/O PB2 (also ADC3_IN10, CMP2_INM2, EIRQ2 and WKUP0_2); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 21 | PB10 | bidirectional | General-purpose I/O PB10 (also ADC3_IN11 and EIRQ10); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 22 | PB11 | bidirectional | General-purpose I/O PB11 (also CMP3_INP1 and EIRQ11); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 23 | VSS | power_in | Ground reference, 0 V. |
| 24 | VCC | power_in | Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme. |
| 25 | PB12 | bidirectional | General-purpose I/O PB12 (also ADC3_IN0 and EIRQ12); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 26 | PB13 | bidirectional | General-purpose I/O PB13 (also ADC3_IN1 and EIRQ13); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 27 | PB14 | bidirectional | General-purpose I/O PB14 (also ADC3_IN2 and EIRQ14); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 28 | PB15 | bidirectional | General-purpose I/O PB15 (also ADC3_IN3, CMP3_INM2, RTC_CLK2 and EIRQ15); 5 V tolerant, and when used as an analog input the voltage must not exceed AVCC/VREFH. |
| 29 | PA8 | bidirectional | General-purpose I/O PA8 (also EXVREF, EIRQ8, WKUP2_0 and TRACED0); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 30 | PA9 | bidirectional | General-purpose I/O PA9 (also EIRQ9 and TRACECLK); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 31 | PA10 | bidirectional | General-purpose I/O PA10 (also EIRQ10, WKUP2_2 and TRACED1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 32 | PA11 | bidirectional | General-purpose I/O PA11 (also EIRQ11, WKUP2_3 and TRACED2); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 33 | PA12 | bidirectional | General-purpose I/O PA12 (also EIRQ12, WKUP3_0, TRACED3 and SPI_NSS1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 34 | PA13 | bidirectional | General-purpose I/O PA13 (also EIRQ13 and JTMS_SWDIO debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 35 | VSS | power_in | Ground reference, 0 V. |
| 36 | VCC | power_in | Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme. |
| 37 | PA14 | bidirectional | General-purpose I/O PA14 (also EIRQ14, WKUP3_2 and JTCK_SWCLK debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 38 | PA15 | bidirectional | General-purpose I/O PA15 (also EIRQ15, WKUP3_3 and JTDI debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 39 | PB3 | bidirectional | General-purpose I/O PB3 (also EIRQ3, WKUP0_3 and JTDO_TRACESWO debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 40 | PB4 | bidirectional | General-purpose I/O PB4 (also EIRQ4, WKUP1_0 and NJTRST debug function); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 41 | PB5 | bidirectional | General-purpose I/O PB5 (also EIRQ5 and WKUP1_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 42 | PB6 | bidirectional | General-purpose I/O PB6 (also EIRQ6 and WKUP1_2; I2C-capable pin); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 43 | PB7 | bidirectional | General-purpose I/O PB7 (also EIRQ7 and WKUP1_3; I2C-capable pin); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 44 | PF3/MD | input | Mode input MD: must be held low when NRST is released, and a 4.7 kΩ pull-down to VSS is recommended; also usable as GPIO PF3. |
| 45 | PB8 | bidirectional | General-purpose I/O PB8 (also EIRQ8 and PVD2EXINP external PVD2 comparison input); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 46 | PB9 | bidirectional | General-purpose I/O PB9 (also EIRQ9 and WKUP2_1); 5 V tolerant, input must not exceed 5 V, and internal pull-up/pull-down must be disabled when the input is above VCC. |
| 47 | VSS | power_in | Ground reference, 0 V. |
| 48 | VCC | power_in | Power supply, 1.8 V to 3.63 V; decouple close to the VSS pin with ceramic capacitors as shown in the power scheme. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 1.8 |  | 3.63 | V |  | 12 |
| Operating temperature range |  | -40 |  | 105 | ℃ |  | 12 |
| SCL frequency | fSCL | 0 |  | 100 | KHz | Standard mode (SM) | 68 |
| SCL frequency | fSCL | 0 |  | 400 | KHz | Fast mode (FM) | 68 |
| SCL frequency | fSCL | 0 |  | 1000 | KHz | Fast mode plus (FM+) | 68 |
| Load capacitance per bus line | Cb |  |  | 400 | pF | Standard mode (SM) | 68 |
| Load capacitance per bus line | Cb |  |  | 550 | pF | Fast mode plus (FM+) | 68 |
| SCL/SDA rise time | tR |  |  | 1000 | ns | Standard mode (SM) | 68 |
| SCL/SDA rise time | tR |  |  | 300 | ns | Fast mode (FM) | 68 |
| SCL/SDA rise time | tR |  |  | 120 | ns | Fast mode plus (FM+) | 68 |
| SCL/SDA fall time | tF |  |  | 300 | ns | Standard mode (SM) | 68 |
| SCL/SDA fall time | tF |  |  | 120 | ns | Fast mode plus (FM+) | 68 |
| START/RESTART condition hold time | tHD;STA | 4 |  |  | μs | Standard mode (SM) | 68 |
| START/RESTART condition hold time | tHD;STA | 0.6 |  |  | μs | Fast mode (FM) | 68 |
| START/RESTART condition hold time | tHD;STA | 0.26 |  |  | μs | Fast mode plus (FM+) | 68 |
| SCL low period | tLOW | 4.7 |  |  | μs | Standard mode (SM) | 68 |
| SCL low period | tLOW | 1.3 |  |  | μs | Fast mode (FM) | 68 |
| SCL low period | tLOW | 0.5 |  |  | μs | Fast mode plus (FM+) | 68 |
| SCL high period | tHIGH | 4 |  |  | μs | Standard mode (SM) | 68 |
| SCL high period | tHIGH | 0.6 |  |  | μs | Fast mode (FM) | 68 |
| SCL high period | tHIGH | 0.26 |  |  | μs | Fast mode plus (FM+) | 68 |
| Repeated START condition setup time | tSU;STA | 4.7 |  |  | μs | Standard mode (SM) | 68 |
| Repeated START condition setup time | tSU;STA | 0.6 |  |  | μs | Fast mode (FM) | 68 |
| Repeated START condition setup time | tSU;STA | 0.26 |  |  | μs | Fast mode plus (FM+) | 68 |
| Data hold time | tHD;DAT | 0 |  |  | μs | Standard mode (SM) | 68 |
| STOP condition setup time | tSU;STO | 4 |  |  | μs | Standard mode (SM) | 68 |
| STOP condition setup time | tSU;STO | 0.6 |  |  | μs | Fast mode (FM) | 68 |
| STOP condition setup time | tSU;STO | 0.26 |  |  | μs | Fast mode plus (FM+) | 68 |
| Bus free time between STOP and START | tBUF | 4.7 |  |  | μs | Standard mode (SM) | 68 |
| Bus free time between STOP and START | tBUF | 1.3 |  |  | μs | Fast mode (FM) | 68 |
| Bus free time between STOP and START | tBUF | 0.5 |  |  | μs | Fast mode plus (FM+) | 68 |
| Slave data input setup time | tsu(SI) | 4 |  |  | ns | Slave mode, 1.8V≤Vcc≤3.63V | 69 |
| Slave data input hold time | th(SI) | 3 |  |  | ns | Slave mode, 1.8V≤Vcc≤3.63V | 69 |
| Slave data output valid time | tv(SO) |  |  | 15 | ns | Slave mode, 2.7V≤Vcc≤3.63V | 69 |
| Slave data output valid time | tv(SO) |  |  | 26 | ns | Slave mode, 1.8V≤Vcc<2.7V | 69 |
| Master data input setup time | tsu(MI) | 5 |  |  | ns | Master mode, 2.7V≤Vcc≤3.63V | 69 |
| Master data input setup time | tsu(MI) | 9 |  |  | ns | Master mode, 1.8V≤Vcc<2.7V | 69 |
| Master data input hold time | th(MI) | 5 |  |  | ns | Master mode, 2.7V≤Vcc≤3.63V | 69 |
| Master data input hold time | th(MI) | 15 |  |  | ns | Master mode, 1.8V≤Vcc≤2.7V | 69 |
| Master data output valid time | tv(MO) |  |  | 4 | ns | Master mode, 2.7V≤Vcc≤3.63V | 69 |
| Master data output valid time | tv(MO) |  |  | 9 | ns | Master mode, 1.8V≤Vcc≤2.7V | 69 |
| Digital external event response time | TLAT(DEEV) |  | 60 | 70 | ns | Synchronous mode; from HRPWMEEVy input to HRPWM_<t>_PWMA/B output, 30pF load | 67 |
| Minimum external event pulse width | TW(EEV) | 12.5 |  |  | ns | Synchronous mode | 67 |
| Analog external event response time | TLAT(AEEV) |  | 75 | 85 | ns | Synchronous mode; from CMPy_INPz input to HRPWM_<t>_PWMA/B output, 30pF load | 67 |
| External event response jitter | TJIT(EEV) |  |  | 1 | tPCLK0 | Synchronous mode; from HRPWM_EEVy input to HRPWM_<t>_PWMA/B output | 67 |
| Synchronous input HRPWM_TRGA~D minimum pulse width | Tw(TRGA-D) | 2 |  |  | tPCLK0 |  | 67 |
| Synchronous request response time | TRES(TRGA-D) |  |  | 4 | tPCLK0 |  | 67 |
| Synchronous output HRPWM_SYNCOUT minimum pulse width | Tw(SYNCOUT) | 16 |  | 65535 | tPCLK0 |  | 67 |

## CAD (KiCad official)

- Symbol: `HC32F334JATI-LQ48`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `hc32f334jati-lq48-etched.step` / `hc32f334jati-lq48-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f334jati-lq48.step` / `hc32f334jati-lq48.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603406208674525184) (102 pp, sha256 `bf3aa4841b430601`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hc32f334jati-lq48-datasheet.pdf)