component
HC32F334J8UI-ZFN48TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), QFN-48-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HC32F334J8UI-ZFN48TR
XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(5x5)
HC32F334J8UI-ZFN48TR from XHSC, in a QFN-48-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | 5 V-tolerant GPIO with EIRQ2 external interrupt and alternate functions such as USART1_CK and TMR6_TRIGB; when used as an input the voltage must not exceed 5 V, and internal pull-up/pull-down must be disabled when the pin is above VCC. |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO with EIRQ13/WKUP3_1 external interrupt and Power-Down wake-up input, plus alternate RTC_OUT (1 Hz clock output); input must not exceed 5 V. |
| 3 | PC14/XTAL32_IN | input | Low-speed 32.768 kHz crystal oscillator input (XTAL32_IN), also usable as 5 V-tolerant GPIO PC14 with EIRQ14; load capacitors must be placed as close to the pin as possible. |
| 4 | PC15/XTAL32_OUT | output | Low-speed 32.768 kHz crystal oscillator output (XTAL32_OUT), also usable as 5 V-tolerant GPIO PC15 with EIRQ15; the resonator and load capacitors must be placed close to the pin. |
| 5 | PF0/XTAL_IN | input | High-speed crystal/ceramic resonator input (XTAL_IN) for a 4 to 25 MHz oscillator, also usable as 5 V-tolerant GPIO PF0 with EIRQ0 and CMP3_OUT. |
| 6 | PF1/XTAL_OUT | output | High-speed crystal/ceramic resonator output (XTAL_OUT) for a 4 to 25 MHz oscillator, also usable as 5 V-tolerant GPIO PF1 with EIRQ1 and CMP1_OUT. |
| 7 | NRST | input | Active-low reset input; if unused it should be pulled up to VCC through a resistor, and the reset pulse must be at least 10 µs wide. |
| 8 | AVSS/VREFL | power_in | Analog ground and low ADC/DAC reference voltage; must be shorted to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply and high ADC/DAC reference voltage, to be held at the same voltage as VCC (1.8 to 3.63 V); must be shorted to VCC when the analog modules are not used. |
| 10 | PA0 | bidirectional | 5 V-tolerant GPIO with EIRQ0/WKUP0_0 wake-up and ADC1_IN0 analog input (analog voltage must not exceed VREFH/AVCC), plus alternates such as CMP1_OUT, FCMREF and TMRA_1_PWM1/CLKA. |
| 11 | PA1 | bidirectional | 5 V-tolerant GPIO with ADC1_IN1 analog input (must not exceed AVCC), RTC_CLK1 external RTC clock input and EIRQ1, plus alternates such as TMR6_TRIGA and TMRA_1_PWM2/CLKB. |
| 12 | PA2 | bidirectional | 5 V-tolerant GPIO with ADC1_IN2 and CMP1_INM2 analog inputs (must not exceed AVCC) and EIRQ2, plus alternates such as ADTRG1, CMP2_OUT and PLA0OUT. |
| 13 | PA3 | bidirectional | 5 V-tolerant GPIO with ADC1_IN3, CMP1_INP2, CMP2_INP2 and CMP3_INP2 analog inputs (must not exceed AVCC) and EIRQ3, plus alternates such as ADTRG2 and TMRA_4_PWM3. |
| 14 | PA4 | bidirectional | 5 V-tolerant GPIO with ADC12_IN4, DAC1_OUT1 and CMP inverting-input analog functions (must not exceed AVCC) and EIRQ4, plus alternates such as USART1_CK, USART2_CK and PLA5OUT. |
| 15 | PA5 | bidirectional | 5 V-tolerant GPIO with ADC12_IN5 and DAC1_OUT2 analog functions (must not exceed AVCC) and EIRQ5, plus alternates such as PLA6OUT and TMRA_5_PWM3. |
| 16 | PA6 | bidirectional | 5 V-tolerant GPIO with ADC123_IN6 and DAC2_OUT1 analog functions (must not exceed AVCC) and EIRQ6, plus alternates such as CMP1_OUT and EMB_PORT1_IN2. |
| 17 | PA7 | bidirectional | 5 V-tolerant GPIO with ADC123_IN7 and CMP1_INP1 analog inputs (must not exceed AVCC) and EIRQ7, plus alternates such as ADTRG3 and CMP2_OUT. |
| 18 | PB0 | bidirectional | 5 V-tolerant GPIO with ADC123_IN8 and CMP2_INP1 analog inputs (must not exceed AVCC) and EIRQ0, plus alternates such as ADTRG1 and RTC_OUT. |
| 19 | PB1 | bidirectional | 5 V-tolerant GPIO with ADC123_IN9 analog input (must not exceed AVCC), EIRQ1/WKUP0_1 wake-up, plus alternates such as ADTRG2, CMP1_OUT and MCO_1. |
| 20 | PB2 | bidirectional | 5 V-tolerant GPIO with ADC3_IN10 and CMP2_INM2 analog inputs (must not exceed AVCC) and EIRQ2/WKUP0_2 wake-up, plus alternates such as ADTRG3 and MCO_2. |
| 21 | PB10 | bidirectional | 5 V-tolerant GPIO with ADC3_IN11 analog input (must not exceed AVCC) and EIRQ10, plus alternates such as HRPWM_EEV9 and EMB_PORT1_IN3. |
| 22 | PB11 | bidirectional | 5 V-tolerant GPIO with CMP3_INP1 analog input (must not exceed AVCC) and EIRQ11, plus alternates such as HRPWM_EEV7 and TMRA_1_PWM4. |
| 23 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 24 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 25 | PB12 | bidirectional | 5 V-tolerant GPIO with ADC3_IN0 analog input (must not exceed AVCC) and EIRQ12, plus alternates such as HRPWM_4_PWMA, USART1_CK and EMB_PORT1_IN1. |
| 26 | PB13 | bidirectional | 5 V-tolerant GPIO with ADC3_IN1 analog input (must not exceed AVCC) and EIRQ13, plus alternates such as HRPWM_4_PWMB and TMRA_4_PWM4. |
| 27 | PB14 | bidirectional | 5 V-tolerant GPIO with ADC3_IN2 analog input (must not exceed AVCC) and EIRQ14, plus alternates such as HRPWM_5_PWMA and TMR4_OUH. |
| 28 | PB15 | bidirectional | 5 V-tolerant GPIO with ADC3_IN3, CMP3_INM2 and RTC_CLK2 functions (analog voltage must not exceed AVCC) and EIRQ15, plus alternates such as CMP1_OUT and HRPWM_5_PWMB. |
| 29 | PA8 | bidirectional | 5 V-tolerant GPIO with EXVREF analog reference input, EIRQ8/WKUP2_0 wake-up and TRACED0 trace data output, plus alternates such as USART2_CK, CTCREF and MCO_1. |
| 30 | PA9 | bidirectional | 5 V-tolerant GPIO with EIRQ9 external interrupt and TRACECLK trace clock output, plus alternates such as EMB_PORT1_IN3 and MCO_2. |
| 31 | PA10 | bidirectional | 5 V-tolerant GPIO with EIRQ10/WKUP2_2 wake-up and TRACED1 trace data output, plus alternates such as CMP3_OUT and TMR4_CLK. |
| 32 | PA11 | bidirectional | 5 V-tolerant GPIO with EIRQ11/WKUP2_3 wake-up and TRACED2 trace data output, plus alternates such as CMP1_OUT and EMB_PORT1_IN2. |
| 33 | PA12 | bidirectional | 5 V-tolerant GPIO with EIRQ12/WKUP3_0 wake-up and TRACED3 trace data output, plus alternates such as CMP2_OUT, SPI_NSS1 and FCMREF. |
| 34 | PA13 | bidirectional | 5 V-tolerant GPIO with EIRQ13 external interrupt and JTMS_SWDIO serial-wire debug data I/O, plus alternates such as USART4_CK and ADTRG3. |
| 35 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 36 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 37 | PA14 | bidirectional | 5 V-tolerant GPIO with EIRQ14/WKUP3_2 wake-up and JTCK_SWCLK serial-wire debug clock input, plus alternates such as ADTRG2 and TMR6_4_PWMB. |
| 38 | PA15 | bidirectional | 5 V-tolerant GPIO with EIRQ15/WKUP3_3 wake-up and JTDI debug data input, plus alternates such as HRPWM_EEV1 and EMB_PORT1_IN2. |
| 39 | PB3 | bidirectional | 5 V-tolerant GPIO with EIRQ3/WKUP0_3 wake-up and JTDO/TRACESWO debug output, plus alternates such as HRPWM_SCOUT and TMR4_OWL. |
| 40 | PB4 | bidirectional | 5 V-tolerant GPIO with EIRQ4/WKUP1_0 wake-up and NJTRST debug reset input, plus alternates such as HRPWM_EEV7 and MCO_2. |
| 41 | PB5 | bidirectional | 5 V-tolerant GPIO with EIRQ5/WKUP1_1 wake-up, plus alternates such as HRPWM_EEV6, USART1_CK and MCO_1. |
| 42 | PB6 | bidirectional | 5 V-tolerant GPIO listed as an I2C pin in the datasheet (I/O pin capacitance 10 pF), with EIRQ6/WKUP1_2 wake-up and alternates such as SPI_NSS2 and CTCREF. |
| 43 | PB7 | bidirectional | 5 V-tolerant GPIO listed as an I2C pin in the datasheet (I/O pin capacitance 10 pF), with EIRQ7/WKUP1_3 wake-up and alternates such as EMB_PORT1_IN1, FCMREF and CMP2_OUT. |
| 44 | PF3/MD | bidirectional | Mode input MD must be held low when NRST is released, with a 4.7 kΩ pull-down to VSS recommended; the pin is also 5 V-tolerant GPIO PF3 with ADTRG3 and alternates. |
| 45 | PB8 | bidirectional | 5 V-tolerant GPIO with EIRQ8 external interrupt and PVD2EXINP external PVD2 comparison voltage input, plus alternates such as SPI_NSS3 and ADTRG1. |
| 46 | PB9 | bidirectional | 5 V-tolerant GPIO with EIRQ9/WKUP2_1 wake-up, plus alternates such as CMP2_OUT, CMP1_OUT and TMR4_ADSM. |
| 47 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating ambient temperature (suffix I) | -40 | 105 | ℃ | 12 | |||
| Power supply voltage range | 1.8 | 3.63 | V | 12 | |||
| HRPWM digital external event response time | TLAT(DEEV) | 60 | 70 | ns | 30pF负载 | 67 | |
| HRPWM minimum external event pulse width | TW(EEV) | 12.5 | ns | 67 | |||
| HRPWM analog external event response time | TLAT(AEEV) | 75 | 85 | ns | 30pF负载 | 67 | |
| HRPWM external event response jitter | TJIT(EEV) | 1 | tPCLK0 | 67 | |||
| HRPWM sync input HRPWM_TRGA~D minimum pulse width | Tw(TRGA-D) | 2 | tPCLK0 | 67 | |||
| HRPWM sync request response time | TRES(TRGA-D) | 4 | tPCLK0 | 67 | |||
| HRPWM sync output HRPWM_SYNCOUT minimum pulse width | Tw(SYNCOUT) | 16 | 65535 | tPCLK0 | 67 | ||
| I2C SCL frequency | fSCL | 0 | 100 | KHz | 标准模式（SM） | 68 | |
| I2C SCL frequency | fSCL | 0 | 400 | KHz | 快速模式（FM） | 68 | |
| I2C SCL frequency | fSCL | 0 | 1000 | KHz | 快速模式Plus（FM+） | 68 | |
| I2C start/restart condition hold time | tHD;STA | 4 | μs | 标准模式（SM） | 68 | ||
| I2C start/restart condition hold time | tHD;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| I2C start/restart condition hold time | tHD;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C SCL low period | tLOW | 4.7 | μs | 标准模式（SM） | 68 | ||
| I2C SCL low period | tLOW | 1.3 | μs | 快速模式（FM） | 68 | ||
| I2C SCL low period | tLOW | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C SCL high period | tHIGH | 4 | μs | 标准模式（SM） | 68 | ||
| I2C SCL high period | tHIGH | 0.6 | μs | 快速模式（FM） | 68 | ||
| I2C SCL high period | tHIGH | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C restart condition setup time | tSU;STA | 4.7 | μs | 标准模式（SM） | 68 | ||
| I2C restart condition setup time | tSU;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| I2C restart condition setup time | tSU;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C data hold time | tHD;DAT | 0 | μs | 标准模式（SM） | 68 | ||
| I2C SCL/SDA rise time | tR | 1000 | ns | 标准模式（SM） | 68 | ||
| I2C SCL/SDA rise time | tR | 300 | ns | 快速模式（FM） | 68 | ||
| I2C SCL/SDA rise time | tR | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| I2C SCL/SDA fall time | tF | 300 | ns | 标准模式（SM） | 68 | ||
| I2C SCL/SDA fall time | tF | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| I2C stop condition setup time | tSU;STO | 4 | μs | 标准模式（SM） | 68 | ||
| I2C stop condition setup time | tSU;STO | 0.6 | μs | 快速模式（FM） | 68 | ||
| I2C stop condition setup time | tSU;STO | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C bus free time between stop and start | tBUF | 4.7 | μs | 标准模式（SM） | 68 | ||
| I2C bus free time between stop and start | tBUF | 1.3 | μs | 快速模式（FM） | 68 | ||
| I2C bus free time between stop and start | tBUF | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| I2C bus load capacitance | Cb | 400 | pF | 标准模式（SM） | 68 | ||
| I2C bus load capacitance | Cb | 550 | pF | 快速模式Plus（FM+） | 68 | ||
| SPI data input setup time (slave) | tsu(SI) | 4 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| SPI data input hold time (slave) | th(SI) | 3 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| SPI data output valid time (slave) | tv(SO) | 15 | ns | 从机模式，2.7V≤Vcc≤3.63V | 69 | ||
| SPI data output valid time (slave) | tv(SO) | 26 | ns | 从机模式，1.8V≤Vcc＜2.7V | 69 | ||
| SPI data input setup time (master) | tsu(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| SPI data input setup time (master) | tsu(MI) | 9 | ns | 主机模式，1.8V≤Vcc＜2.7V | 69 | ||
| SPI data input hold time (master) | th(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| SPI data input hold time (master) | th(MI) | 15 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 | ||
| SPI data output valid time (master) | tv(MO) | 4 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| SPI data output valid time (master) | tv(MO) | 9 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
CAD (KiCad official)
- Symbol:
HC32F334J8UI-ZFN48TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm - 3D model: QFN-48-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
hc32f334j8ui-zfn48tr-etched.step/hc32f334j8ui-zfn48tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f334j8ui-zfn48tr.step/hc32f334j8ui-zfn48tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (102 pp, sha256
bf3aa4841b430601, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HC32F334J8UI-ZFN48TR
**XHSC** · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(5x5)
HC32F334J8UI-ZFN48TR from XHSC, in a QFN-48-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | 5 V-tolerant GPIO with EIRQ2 external interrupt and alternate functions such as USART1_CK and TMR6_TRIGB; when used as an input the voltage must not exceed 5 V, and internal pull-up/pull-down must be disabled when the pin is above VCC. |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO with EIRQ13/WKUP3_1 external interrupt and Power-Down wake-up input, plus alternate RTC_OUT (1 Hz clock output); input must not exceed 5 V. |
| 3 | PC14/XTAL32_IN | input | Low-speed 32.768 kHz crystal oscillator input (XTAL32_IN), also usable as 5 V-tolerant GPIO PC14 with EIRQ14; load capacitors must be placed as close to the pin as possible. |
| 4 | PC15/XTAL32_OUT | output | Low-speed 32.768 kHz crystal oscillator output (XTAL32_OUT), also usable as 5 V-tolerant GPIO PC15 with EIRQ15; the resonator and load capacitors must be placed close to the pin. |
| 5 | PF0/XTAL_IN | input | High-speed crystal/ceramic resonator input (XTAL_IN) for a 4 to 25 MHz oscillator, also usable as 5 V-tolerant GPIO PF0 with EIRQ0 and CMP3_OUT. |
| 6 | PF1/XTAL_OUT | output | High-speed crystal/ceramic resonator output (XTAL_OUT) for a 4 to 25 MHz oscillator, also usable as 5 V-tolerant GPIO PF1 with EIRQ1 and CMP1_OUT. |
| 7 | NRST | input | Active-low reset input; if unused it should be pulled up to VCC through a resistor, and the reset pulse must be at least 10 µs wide. |
| 8 | AVSS/VREFL | power_in | Analog ground and low ADC/DAC reference voltage; must be shorted to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply and high ADC/DAC reference voltage, to be held at the same voltage as VCC (1.8 to 3.63 V); must be shorted to VCC when the analog modules are not used. |
| 10 | PA0 | bidirectional | 5 V-tolerant GPIO with EIRQ0/WKUP0_0 wake-up and ADC1_IN0 analog input (analog voltage must not exceed VREFH/AVCC), plus alternates such as CMP1_OUT, FCMREF and TMRA_1_PWM1/CLKA. |
| 11 | PA1 | bidirectional | 5 V-tolerant GPIO with ADC1_IN1 analog input (must not exceed AVCC), RTC_CLK1 external RTC clock input and EIRQ1, plus alternates such as TMR6_TRIGA and TMRA_1_PWM2/CLKB. |
| 12 | PA2 | bidirectional | 5 V-tolerant GPIO with ADC1_IN2 and CMP1_INM2 analog inputs (must not exceed AVCC) and EIRQ2, plus alternates such as ADTRG1, CMP2_OUT and PLA0OUT. |
| 13 | PA3 | bidirectional | 5 V-tolerant GPIO with ADC1_IN3, CMP1_INP2, CMP2_INP2 and CMP3_INP2 analog inputs (must not exceed AVCC) and EIRQ3, plus alternates such as ADTRG2 and TMRA_4_PWM3. |
| 14 | PA4 | bidirectional | 5 V-tolerant GPIO with ADC12_IN4, DAC1_OUT1 and CMP inverting-input analog functions (must not exceed AVCC) and EIRQ4, plus alternates such as USART1_CK, USART2_CK and PLA5OUT. |
| 15 | PA5 | bidirectional | 5 V-tolerant GPIO with ADC12_IN5 and DAC1_OUT2 analog functions (must not exceed AVCC) and EIRQ5, plus alternates such as PLA6OUT and TMRA_5_PWM3. |
| 16 | PA6 | bidirectional | 5 V-tolerant GPIO with ADC123_IN6 and DAC2_OUT1 analog functions (must not exceed AVCC) and EIRQ6, plus alternates such as CMP1_OUT and EMB_PORT1_IN2. |
| 17 | PA7 | bidirectional | 5 V-tolerant GPIO with ADC123_IN7 and CMP1_INP1 analog inputs (must not exceed AVCC) and EIRQ7, plus alternates such as ADTRG3 and CMP2_OUT. |
| 18 | PB0 | bidirectional | 5 V-tolerant GPIO with ADC123_IN8 and CMP2_INP1 analog inputs (must not exceed AVCC) and EIRQ0, plus alternates such as ADTRG1 and RTC_OUT. |
| 19 | PB1 | bidirectional | 5 V-tolerant GPIO with ADC123_IN9 analog input (must not exceed AVCC), EIRQ1/WKUP0_1 wake-up, plus alternates such as ADTRG2, CMP1_OUT and MCO_1. |
| 20 | PB2 | bidirectional | 5 V-tolerant GPIO with ADC3_IN10 and CMP2_INM2 analog inputs (must not exceed AVCC) and EIRQ2/WKUP0_2 wake-up, plus alternates such as ADTRG3 and MCO_2. |
| 21 | PB10 | bidirectional | 5 V-tolerant GPIO with ADC3_IN11 analog input (must not exceed AVCC) and EIRQ10, plus alternates such as HRPWM_EEV9 and EMB_PORT1_IN3. |
| 22 | PB11 | bidirectional | 5 V-tolerant GPIO with CMP3_INP1 analog input (must not exceed AVCC) and EIRQ11, plus alternates such as HRPWM_EEV7 and TMRA_1_PWM4. |
| 23 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 24 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 25 | PB12 | bidirectional | 5 V-tolerant GPIO with ADC3_IN0 analog input (must not exceed AVCC) and EIRQ12, plus alternates such as HRPWM_4_PWMA, USART1_CK and EMB_PORT1_IN1. |
| 26 | PB13 | bidirectional | 5 V-tolerant GPIO with ADC3_IN1 analog input (must not exceed AVCC) and EIRQ13, plus alternates such as HRPWM_4_PWMB and TMRA_4_PWM4. |
| 27 | PB14 | bidirectional | 5 V-tolerant GPIO with ADC3_IN2 analog input (must not exceed AVCC) and EIRQ14, plus alternates such as HRPWM_5_PWMA and TMR4_OUH. |
| 28 | PB15 | bidirectional | 5 V-tolerant GPIO with ADC3_IN3, CMP3_INM2 and RTC_CLK2 functions (analog voltage must not exceed AVCC) and EIRQ15, plus alternates such as CMP1_OUT and HRPWM_5_PWMB. |
| 29 | PA8 | bidirectional | 5 V-tolerant GPIO with EXVREF analog reference input, EIRQ8/WKUP2_0 wake-up and TRACED0 trace data output, plus alternates such as USART2_CK, CTCREF and MCO_1. |
| 30 | PA9 | bidirectional | 5 V-tolerant GPIO with EIRQ9 external interrupt and TRACECLK trace clock output, plus alternates such as EMB_PORT1_IN3 and MCO_2. |
| 31 | PA10 | bidirectional | 5 V-tolerant GPIO with EIRQ10/WKUP2_2 wake-up and TRACED1 trace data output, plus alternates such as CMP3_OUT and TMR4_CLK. |
| 32 | PA11 | bidirectional | 5 V-tolerant GPIO with EIRQ11/WKUP2_3 wake-up and TRACED2 trace data output, plus alternates such as CMP1_OUT and EMB_PORT1_IN2. |
| 33 | PA12 | bidirectional | 5 V-tolerant GPIO with EIRQ12/WKUP3_0 wake-up and TRACED3 trace data output, plus alternates such as CMP2_OUT, SPI_NSS1 and FCMREF. |
| 34 | PA13 | bidirectional | 5 V-tolerant GPIO with EIRQ13 external interrupt and JTMS_SWDIO serial-wire debug data I/O, plus alternates such as USART4_CK and ADTRG3. |
| 35 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 36 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 37 | PA14 | bidirectional | 5 V-tolerant GPIO with EIRQ14/WKUP3_2 wake-up and JTCK_SWCLK serial-wire debug clock input, plus alternates such as ADTRG2 and TMR6_4_PWMB. |
| 38 | PA15 | bidirectional | 5 V-tolerant GPIO with EIRQ15/WKUP3_3 wake-up and JTDI debug data input, plus alternates such as HRPWM_EEV1 and EMB_PORT1_IN2. |
| 39 | PB3 | bidirectional | 5 V-tolerant GPIO with EIRQ3/WKUP0_3 wake-up and JTDO/TRACESWO debug output, plus alternates such as HRPWM_SCOUT and TMR4_OWL. |
| 40 | PB4 | bidirectional | 5 V-tolerant GPIO with EIRQ4/WKUP1_0 wake-up and NJTRST debug reset input, plus alternates such as HRPWM_EEV7 and MCO_2. |
| 41 | PB5 | bidirectional | 5 V-tolerant GPIO with EIRQ5/WKUP1_1 wake-up, plus alternates such as HRPWM_EEV6, USART1_CK and MCO_1. |
| 42 | PB6 | bidirectional | 5 V-tolerant GPIO listed as an I2C pin in the datasheet (I/O pin capacitance 10 pF), with EIRQ6/WKUP1_2 wake-up and alternates such as SPI_NSS2 and CTCREF. |
| 43 | PB7 | bidirectional | 5 V-tolerant GPIO listed as an I2C pin in the datasheet (I/O pin capacitance 10 pF), with EIRQ7/WKUP1_3 wake-up and alternates such as EMB_PORT1_IN1, FCMREF and CMP2_OUT. |
| 44 | PF3/MD | bidirectional | Mode input MD must be held low when NRST is released, with a 4.7 kΩ pull-down to VSS recommended; the pin is also 5 V-tolerant GPIO PF3 with ADTRG3 and alternates. |
| 45 | PB8 | bidirectional | 5 V-tolerant GPIO with EIRQ8 external interrupt and PVD2EXINP external PVD2 comparison voltage input, plus alternates such as SPI_NSS3 and ADTRG1. |
| 46 | PB9 | bidirectional | 5 V-tolerant GPIO with EIRQ9/WKUP2_1 wake-up, plus alternates such as CMP2_OUT, CMP1_OUT and TMR4_ADSM. |
| 47 | VSS | power_in | Ground reference (0 V); the difference between any VSSx pin and VSS must not exceed 50 mV. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.63 V, decoupled close to the pin with 0.1 µF and with a 4.7 µF ceramic capacitor on one VCC pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating ambient temperature (suffix I) | | -40 | | 105 | ℃ | | 12 |
| Power supply voltage range | | 1.8 | | 3.63 | V | | 12 |
| HRPWM digital external event response time | TLAT(DEEV) | | 60 | 70 | ns | 30pF负载 | 67 |
| HRPWM minimum external event pulse width | TW(EEV) | 12.5 | | | ns | | 67 |
| HRPWM analog external event response time | TLAT(AEEV) | | 75 | 85 | ns | 30pF负载 | 67 |
| HRPWM external event response jitter | TJIT(EEV) | | | 1 | tPCLK0 | | 67 |
| HRPWM sync input HRPWM_TRGA~D minimum pulse width | Tw(TRGA-D) | 2 | | | tPCLK0 | | 67 |
| HRPWM sync request response time | TRES(TRGA-D) | | | 4 | tPCLK0 | | 67 |
| HRPWM sync output HRPWM_SYNCOUT minimum pulse width | Tw(SYNCOUT) | 16 | | 65535 | tPCLK0 | | 67 |
| I2C SCL frequency | fSCL | 0 | | 100 | KHz | 标准模式（SM） | 68 |
| I2C SCL frequency | fSCL | 0 | | 400 | KHz | 快速模式（FM） | 68 |
| I2C SCL frequency | fSCL | 0 | | 1000 | KHz | 快速模式Plus（FM+） | 68 |
| I2C start/restart condition hold time | tHD;STA | 4 | | | μs | 标准模式（SM） | 68 |
| I2C start/restart condition hold time | tHD;STA | 0.6 | | | μs | 快速模式（FM） | 68 |
| I2C start/restart condition hold time | tHD;STA | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C SCL low period | tLOW | 4.7 | | | μs | 标准模式（SM） | 68 |
| I2C SCL low period | tLOW | 1.3 | | | μs | 快速模式（FM） | 68 |
| I2C SCL low period | tLOW | 0.5 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C SCL high period | tHIGH | 4 | | | μs | 标准模式（SM） | 68 |
| I2C SCL high period | tHIGH | 0.6 | | | μs | 快速模式（FM） | 68 |
| I2C SCL high period | tHIGH | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C restart condition setup time | tSU;STA | 4.7 | | | μs | 标准模式（SM） | 68 |
| I2C restart condition setup time | tSU;STA | 0.6 | | | μs | 快速模式（FM） | 68 |
| I2C restart condition setup time | tSU;STA | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C data hold time | tHD;DAT | 0 | | | μs | 标准模式（SM） | 68 |
| I2C SCL/SDA rise time | tR | | | 1000 | ns | 标准模式（SM） | 68 |
| I2C SCL/SDA rise time | tR | | | 300 | ns | 快速模式（FM） | 68 |
| I2C SCL/SDA rise time | tR | | | 120 | ns | 快速模式Plus（FM+） | 68 |
| I2C SCL/SDA fall time | tF | | | 300 | ns | 标准模式（SM） | 68 |
| I2C SCL/SDA fall time | tF | | | 120 | ns | 快速模式Plus（FM+） | 68 |
| I2C stop condition setup time | tSU;STO | 4 | | | μs | 标准模式（SM） | 68 |
| I2C stop condition setup time | tSU;STO | 0.6 | | | μs | 快速模式（FM） | 68 |
| I2C stop condition setup time | tSU;STO | 0.26 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C bus free time between stop and start | tBUF | 4.7 | | | μs | 标准模式（SM） | 68 |
| I2C bus free time between stop and start | tBUF | 1.3 | | | μs | 快速模式（FM） | 68 |
| I2C bus free time between stop and start | tBUF | 0.5 | | | μs | 快速模式Plus（FM+） | 68 |
| I2C bus load capacitance | Cb | | | 400 | pF | 标准模式（SM） | 68 |
| I2C bus load capacitance | Cb | | | 550 | pF | 快速模式Plus（FM+） | 68 |
| SPI data input setup time (slave) | tsu(SI) | 4 | | | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 |
| SPI data input hold time (slave) | th(SI) | 3 | | | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 |
| SPI data output valid time (slave) | tv(SO) | | | 15 | ns | 从机模式，2.7V≤Vcc≤3.63V | 69 |
| SPI data output valid time (slave) | tv(SO) | | | 26 | ns | 从机模式，1.8V≤Vcc＜2.7V | 69 |
| SPI data input setup time (master) | tsu(MI) | 5 | | | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| SPI data input setup time (master) | tsu(MI) | 9 | | | ns | 主机模式，1.8V≤Vcc＜2.7V | 69 |
| SPI data input hold time (master) | th(MI) | 5 | | | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| SPI data input hold time (master) | th(MI) | 15 | | | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
| SPI data output valid time (master) | tv(MO) | | | 4 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 |
| SPI data output valid time (master) | tv(MO) | | | 9 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 |
## CAD (KiCad official)
- Symbol: `HC32F334J8UI-ZFN48TR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm`
- 3D model: QFN-48-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `hc32f334j8ui-zfn48tr-etched.step` / `hc32f334j8ui-zfn48tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f334j8ui-zfn48tr.step` / `hc32f334j8ui-zfn48tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603406373690351616) (102 pp, sha256 `bf3aa4841b430601`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hc32f334j8ui-zfn48tr-datasheet.pdf)