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Contents

README

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HC32F196PCTA-LQFP100

HDSC · HDSC · LQFP-100(14x14)

HC32F196PCTA-LQFP100 from HDSC, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE02 bidirectional General-purpose I/O port E bit 2 with PCA_ECI digital function.
2 PE03 bidirectional General-purpose I/O port E bit 3 with PCA_CH0 digital function.
3 PE04 bidirectional General-purpose I/O port E bit 4 with PCA_CH1 digital function.
4 PE05 bidirectional General-purpose I/O port E bit 5 with PCA_CH2 digital function.
5 PE06 bidirectional General-purpose I/O port E bit 6 with PCA_CH3 digital function.
6 VCAP passive LDO core supply output for internal circuits only, requires an external decoupling capacitor of at least 1uF.
7 PC13 bidirectional General-purpose I/O port C bit 13 with TIM3_CH1B digital function and LVD0 analog input.
8 XTLI/PC14 bidirectional Port C bit 14 I/O or low-speed (32.768kHz) crystal oscillator input XTLI.
9 XTLO/PC15 bidirectional Port C bit 15 I/O or low-speed (32.768kHz) crystal oscillator output XTLO.
10 PF09 bidirectional General-purpose I/O port F bit 9 with TIM0_CHA digital function.
11 PF10 bidirectional General-purpose I/O port F bit 10 with TIM0_CHB digital function.
12 XTHI/PF00 bidirectional Port F bit 0 I/O (I2C0_SDA, UART1_TXD) or high-speed (4-32MHz) crystal oscillator input XTHI.
13 XTHO/PF01 bidirectional Port F bit 1 I/O (I2C0_SCL, TIM4_CHB, UART1_RXD) or high-speed (4-32MHz) crystal oscillator output XTHO.
14 RESETB input Active-low reset input with non-removable weak pull-up of about 80kOhm.
15 SEG27/PC00 bidirectional Port C bit 0 I/O (UART1_CTS, UART2_RTS) with AIN10, VC0_INP0, VC1_INN0 analog inputs and LCD SEG27.
16 SEG26/PC01 bidirectional Port C bit 1 I/O (TIM5_CHB, UART1_RTS, UART2_CTS) with AIN11, VC0_INP1, VC1_INN1 analog inputs and LCD SEG26.
17 SEG25/PC02 bidirectional Port C bit 2 I/O (SPI1_MISO, UART2_RXD) with AIN12, VC0_INP2, VC1_INN2 analog inputs and LCD SEG25.
18 SEG24/PC03 bidirectional Port C bit 3 I/O (SPI1_MOSI, UART2_TXD) with AIN13, VC0_INP3, VC1_INN3 analog inputs and LCD SEG24.
19 PF02 bidirectional General-purpose I/O port F bit 2.
20 AVSS power_in Analog ground.
21 AVCC power_in Analog supply, must be at the same voltage as DVCC (1.8 to 5.5V).
22 PF03 bidirectional General-purpose I/O port F bit 3.
23 SEG23/PA00 bidirectional Port A bit 0 I/O (UART1_CTS, TIM0_ETR, VC0_OUT, TIM1_CHA, TIM3_ETR, TIM0_CHA) with AIN0 analog input and LCD SEG23.
24 SEG22/PA01 bidirectional Port A bit 1 I/O (UART1_RTS, TIM0_CHB, TIM1_ETR, TIM1_CHB, HCLK_OUT, SPI1_MOSI) with AIN1 analog input and LCD SEG22.
25 SEG21/PA02 bidirectional Port A bit 2 I/O (UART1_TXD, TIM0_CHA, VC1_OUT, TIM1_CHA, TIM2_CHA, PCLK_OUT, SPI1_MISO) with AIN2 analog input and LCD SEG21.
26 SEG20/PA03 bidirectional Port A bit 3 I/O (UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A, TIM5_CHA) with AIN3 analog input and LCD SEG20.
27 DVSS power_in Digital ground.
28 DVCC power_in Digital supply, 1.8 to 5.5V.
29 SEG19/PA04 bidirectional Port A bit 4 I/O (SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT, TIM3_CH2B) with AIN4, DAC_OUT, OPA_OUT0 analog functions and LCD SEG19.
30 SEG18/PA05 bidirectional Port A bit 5 I/O (SPI0_SCK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT, XTH_OUT) with LCD SEG18.
31 SEG17/PA06 bidirectional Port A bit 6 I/O (SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT, TIM3_GATE) with LCD SEG17.
32 SEG16/PA07 bidirectional Port A bit 7 I/O (SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT, TIM4_CHB) with LCD SEG16.
33 SEG15/PC04 bidirectional Port C bit 4 I/O (TIM2_ETR, IR_OUT, VC2_OUT) with LCD SEG15.
34 SEG14/PC05 bidirectional Port C bit 5 I/O (TIM6_CHB, PCA_CH4) with LCD SEG14.
35 SEG13/PB00 bidirectional Port B bit 0 I/O (PCA_CH2, TIM3_CH1B, TIM5_CHB, RCH_OUT, RCL_OUT, PLL_OUT) with LCD SEG13.
36 SEG12/PB01 bidirectional Port B bit 1 I/O (PCA_CH3, PCLK_OUT, TIM3_CH2B, TIM6_CHB, VC2_OUT, TCLK_OUT) with LCD SEG12.
37 SEG11/PB02 bidirectional Port B bit 2 I/O (PCA_ECI, TIM4_CHA, TIM1_BK, TIM0_BK, TIM2_BK) with LCD SEG11.
38 PE07 bidirectional General-purpose I/O port E bit 7 with TIM3_ETR digital function.
39 PE08 bidirectional General-purpose I/O port E bit 8 with TIM3_CH0B digital function.
40 PE09 bidirectional General-purpose I/O port E bit 9 with TIM3_CH0A digital function.
41 PE10 bidirectional General-purpose I/O port E bit 10 with TIM3_CH1B digital function.
42 PE11 bidirectional General-purpose I/O port E bit 11 with TIM3_CH1A digital function.
43 SEG51/PE12 bidirectional Port E bit 12 I/O (TIM3_CH2B, SPI0_CS, UART3_CTS) with LCD SEG51.
44 SEG50/PE13 bidirectional Port E bit 13 I/O (TIM3_CH2A, SPI0_SCK, UART3_RTS) with LCD SEG50.
45 SEG49/PE14 bidirectional Port E bit 14 I/O (TIM3_CH0B, SPI0_MISO, UART3_RXD) with LCD SEG49.
46 SEG48/PE15 bidirectional Port E bit 15 I/O (TIM3_BK, SPI0_MOSI, UART3_TXD) with LCD SEG48.
47 SEG10/PB10 bidirectional Port B bit 10 I/O (I2C1_SCL, SPI1_SCK, TIM1_CHA, TIM3_CH1A, UART1_RTS) with LCD SEG10.
48 SEG9/PB11 bidirectional Port B bit 11 I/O (I2C1_SDA, TIM1_CHB, TIM2_GATE, TIM6_CHA, UART1_CTS) with LCD SEG9.
49 DVSS power_in Digital ground.
50 DVCC power_in Digital supply, 1.8 to 5.5V.
51 PB12/SEG8 bidirectional Port B bit 12 I/O (SPI1_CS, TIM3_BK, TIM0_BK, TIM6_CHA) with LCD SEG8.
52 PB13/SEG7 bidirectional Port B bit 13 I/O (SPI1_SCK, I2C1_SCL, TIM3_CH0B, TIM1_CHA, TIM1_GATE, TIM6_CHB) with LCD SEG7.
53 PB14/SEG6 bidirectional Port B bit 14 I/O (SPI1_MISO, I2C1_SDA, TIM3_CH1B, TIM0_CHA, TIM1_BK) with LCD SEG6.
54 PB15/SEG5 bidirectional Port B bit 15 I/O (SPI1_MOSI, TIM3_CH2B, TIM0_CHB, TIM0_GATE) with LCD SEG5.
55 PD08/SEG47 bidirectional General-purpose I/O port D bit 8 with LCD SEG47.
56 PD09/SEG46 bidirectional General-purpose I/O port D bit 9 with LCD SEG46.
57 PD10/SEG45 bidirectional General-purpose I/O port D bit 10 with LCD SEG45.
58 PD11/SEG44 bidirectional General-purpose I/O port D bit 11 with LCD SEG44.
59 PD12/SEG43 bidirectional Port D bit 12 I/O (UART2_RTS) with LCD SEG43.
60 PD13/SEG42 bidirectional Port D bit 13 I/O (UART2_RXD) with LCD SEG42.
61 PD14/SEG41 bidirectional Port D bit 14 I/O (UART2_TXD) with LCD SEG41.
62 PD15/SEG40 bidirectional Port D bit 15 I/O (UART2_CTS) with LCD SEG40.
63 PC06/SEG4 bidirectional Port C bit 6 I/O (PCA_CH0, TIM4_CHA, TIM2_CHA, UART3_RXD) with LCD SEG4.
64 PC07/SEG3 bidirectional Port C bit 7 I/O (PCA_CH1, TIM5_CHA, TIM2_CHB, UART3_TXD) with LCD SEG3.
65 PC08/SEG2 bidirectional Port C bit 8 I/O (PCA_CH2, TIM6_CHA, TIM2_ETR, UART3_CTS) with LCD SEG2.
66 PC09/SEG1 bidirectional Port C bit 9 I/O (PCA_CH3, TIM4_CHB, TIM1_ETR, UART3_RTS) with LCD SEG1.
67 PA08/SEG0 bidirectional Port A bit 8 I/O (UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA, TIM3_BK) with LCD SEG0.
68 PA09/COM0 bidirectional Port A bit 9 I/O (UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT, TIM5_CHA) with LCD COM0.
69 PA10/COM1 bidirectional Port A bit 10 I/O (UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT, TIM6_CHA) with LCD COM1.
70 PA11/COM2 bidirectional Port A bit 11 I/O (UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO, TIM4_CHB) with LCD COM2.
71 PA12/COM3 bidirectional Port A bit 12 I/O (UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT, SPI0_MOSI) with LCD COM3.
72 PA13/SWDIO bidirectional Port A bit 13 I/O, also the SWD debug data line SWDIO (IR_OUT, UART0_RXD, LVD_OUT, TIM3_ETR, VC2_OUT).
73 PF06 bidirectional Port F bit 6 I/O (I2C1_SCL, UART0_CTS).
74 DVSS power_in Digital ground.
75 DVCC power_in Digital supply, 1.8 to 5.5V.
76 PA14/SWCLK bidirectional Port A bit 14 I/O, also the SWD debug clock SWCLK (UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT, PLL_OUT).
77 PA15 bidirectional Port A bit 15 I/O (SPI0_CS, UART1_RXD, TIM0_ETR, TIM0_CHA, TIM3_CH1A).
78 PC10/COM4/SEG39 bidirectional Port C bit 10 I/O (PCA_CH2) with LCD COM4 or SEG39.
79 PC11/COM5/SEG38 bidirectional Port C bit 11 I/O (PCA_CH3) with LCD COM5 or SEG38.
80 PC12/COM6/SEG37 bidirectional Port C bit 12 I/O (PCA_CH4) with LCD COM6 or SEG37.
81 PD00 bidirectional Port D bit 0 I/O (SPI1_CS).
82 PD01 bidirectional Port D bit 1 I/O (SPI1_SCK).
83 PD02/COM7/SEG36 bidirectional Port D bit 2 I/O (PCA_ECI, TIM1_ETR) with LCD COM7 or SEG36.
84 PD03 bidirectional Port D bit 3 I/O (UART1_CTS, SPI1_MISO).
85 PD04 bidirectional Port D bit 4 I/O (UART1_RTS, SPI1_MOSI).
86 PD05 bidirectional Port D bit 5 I/O (UART1_TXD).
87 PD06 bidirectional Port D bit 6 I/O (UART1_RXD).
88 PD07 bidirectional Port D bit 7 I/O (UART1_TXD).
89 PB03/SEG35/VLCDH bidirectional Port B bit 3 I/O (SPI0_SCK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, XTL_OUT, XTH_OUT) with LCD SEG35 or VLCDH.
90 PB04/SEG34/VLCD3 bidirectional Port B bit 4 I/O (SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B) with LCD SEG34 or VLCD3.
91 PB05/SEG33/VLCD2 bidirectional Port B bit 5 I/O (SPI0_MOSI, TIM1_BK, PCA_CH1, UART0_RTS) with LCD SEG33 or VLCD2.
92 PB06/SEG32/VLCD1 bidirectional Port B bit 6 I/O (I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA, TIM3_CH0A) with LCD SEG32 or VLCD1.
93 PB07/SEG31 bidirectional Port B bit 7 I/O (I2C0_SDA, UART0_RXD, TIM2_CHB, TIM0_CHB) with LCD SEG31; also an LVD monitor source.
94 BOOT0 input Boot mode select (PF11): high at reset enters ISP programming mode, low at reset runs user Flash code.
95 PB08/SEG29 bidirectional Port B bit 8 I/O (I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, TIM3_CH2A, UART0_TXD) with LCD SEG29; also an LVD monitor source.
96 PB09/SEG28 bidirectional Port B bit 9 I/O (I2C0_SDA, IR_OUT, SPI1_CS, TIM2_CHA, TIM2_CHB, UART0_RXD) with LCD SEG28.
97 PE00 bidirectional General-purpose I/O port E bit 0 with TIM1_CHA digital function.
98 PE01 bidirectional General-purpose I/O port E bit 1 with TIM2_CHA digital function.
99 DVSS power_in Digital ground.
100 DVCC power_in Digital supply, 1.8 to 5.5V.

Key specifications

Parameter Value
Manufacturer HDSC
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (including AVCC and DVCC) VCC - VSS -0.3 5.5 V 46
Voltage difference between different supply pins /ΔVCCx/ 50 mV 46
Voltage difference between different ground pins /VSSx - VSS/ 50 mV 46
Total current into DVCC/AVCC power lines (supply) IVCC 300 mA 46
Total current out of VSS ground lines (sink) IVSS 300 mA 46
Output sink current on any I/O and control pin IIO 25 mA 46
Output current on any I/O and control pin IIO -25 mA 46
Injected current on RESETB pin IINJ(PIN) -5 5 mA 46
Injected current on XTHI and XTLI pins IINJ(PIN) -5 5 mA 46
Injected current on other pins IINJ(PIN) -5 5 mA 46
Total injected current on all I/O and control pins ΣIINJ(PIN) -25 25 mA 46
Internal 2.5V reference voltage VREF25 2.475 2.5 2.525 V 25°C, 3.3V 51
Internal 2.5V reference voltage VREF25 2.463 2.5 2.525 V -40 ~ 85°C, 2.8~5.5V 51
Internal 1.5V reference voltage VREF15 1.485 1.5 1.515 V 25°C, 3.3V 51
Internal 1.5V reference voltage VREF15 1.477 1.5 1.519 V -40 ~ 85°C, 1.8~5.5V 51
Reference voltage temperature coefficient TCoeff 120 ppm/°C -40 ~ 85°C 51
External input voltage range (LVD) Vex 0 V max printed as VCC 50
LVD power consumption Icomp 0.12 μA 50
LVD response time Tresponse 80 μs 50
LVD setup time Tsetup 400 μs 50
LVD hysteresis voltage Vhyste 40 mV 50
IDD run, all peripherals ON, while(1) in Flash, RCH 4M IDD 1000 1440 μA VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 52
IDD run, all peripherals ON, while(1) in Flash, RCH 24M IDD 5400 7570 μA VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 52
IDD run, all peripherals ON, while(1) in Flash, PLL 48M IDD 9610 11200 μA RCH4M PLL, FlashWait=1, VCC=1.8-5.5V, TA=-40~85°C 52
IDD run, all peripherals OFF, while(1) in Flash, RCH 4M IDD 610 1000 μA VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 52
IDD run, all peripherals OFF, while(1) in Flash, RCH 24M IDD 2970 4810 μA VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 52

CAD (KiCad official)

  • Symbol: HC32F196PCTA-LQFP100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: hc32f196pcta-lqfp100-etched.step / hc32f196pcta-lqfp100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32f196pcta-lqfp100.step / hc32f196pcta-lqfp100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HDSC datasheet (95 pp, sha256 386469d475dde548, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF