# HC32F002C4UB-ZFN20TR

**XHSC** · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(3x3)

HC32F002C4UB-ZFN20TR from XHSC, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESETB/PA00 | input | Active-low external reset input with internal pull-up and glitch filter; a low level must last more than 20 µs (typ.) to reliably reset the MCU, and PA00 has no alternate digital functions. |
| 2 | PA01 | bidirectional | GPIO PA01 with alternate functions LPUART0_RXD, I2C_SDA, GTIM_TOGP and HCLK_OUT, and ADC input AIN7; it can also be used as the external clock input (1-16 MHz) when SysCtrl.CR2.EXTEN is set. |
| 3 | PA02 | bidirectional | GPIO PA02 with alternate functions LPUART0_TXD, I2C_SCL, GTIM_TOGN and LVD_OUT, and ADC input AIN8. |
| 4 | AVSS/DVSS | power_in | Analog and digital ground, both tied to this pin on the package; must be connected to the external supply ground. |
| 5 | PA04 | bidirectional | GPIO PA04 with alternate functions GTIM_TOGP, LVD_OUT and SPI_NSS. |
| 6 | AVCC/DVCC | power_in | Analog and digital supply, tied together on this pin; the datasheet specifies 1.7-5.5 V operation, requires AVCC and DVCC at the same voltage, and needs decoupling placed close to the pin. |
| 7 | PA03 | bidirectional | GPIO PA03 with alternate functions GTIM_CH2, SPI_NSS, CTRIM_ETR, CTRIM_TOG, and LVD monitor input LVD_IN0. |
| 8 | PB05 | bidirectional | GPIO PB05 with alternate functions I2C_SDA, ATIM3_BK, CTRIM_ETR and CTRIM_TOG, and ADC input AIN9. |
| 9 | PB04 | bidirectional | GPIO PB04 with alternate functions I2C_SCL, ATIM3_CH2B and LPUART0_CTS, and ADC input AIN10; PB04-PB05 and PC03-PC04 have double drive capability in this package. |
| 10 | PC03 | bidirectional | GPIO PC03 with alternate functions ATIM3_CH2A, ATIM3_CH0B and LPUART0_RTS, LVD monitor input LVD_IN1, and ADC external reference input ADC_ExRef. |
| 11 | PC04 | bidirectional | GPIO PC04 with alternate functions ATIM3_CH0B, ATIM3_CH1B and TCLK_OUT, and ADC input AIN0. |
| 12 | PC05 | bidirectional | GPIO PC05 with alternate functions SPI_SCK, GTIM_CH3 and ATIM3_ETR. |
| 13 | PC06 | bidirectional | GPIO PC06 with alternate functions SPI_MOSI, ATIM3_CH0A and LPUART1_RTS, and ADC input AIN1; it is a digital input without pull-up after reset. |
| 14 | PC07 | bidirectional | GPIO PC07 that is the SWDIO debug data pin by default (input with pull-up after reset), with alternate functions SPI_MISO, ATIM3_CH1A and LPUART0_RXD; SWD can be released to GPIO via SysCtrl.CR1.SWDIO. |
| 15 | PD01 | bidirectional | GPIO PD01 that is the SWCLK debug clock pin by default (input with pull-up after reset), with alternate functions GTIM_ETR, ATIM3_BK and LPUART0_TXD; SWD can be released to GPIO via SysCtrl.CR1.SWDIO. |
| 16 | PD02 | bidirectional | GPIO PD02 with alternate functions GTIM_CH2, ATIM3_CH2A and LPUART1_CTS, and ADC input AIN2. |
| 17 | PD03 | bidirectional | GPIO PD03 with alternate functions GTIM_CH1, ATIM3_CH1A and LPUART1_RXD, and ADC input AIN3. |
| 18 | PD04 | bidirectional | GPIO PD04 with alternate functions GTIM_CH0, LPUART1_TXD and SPI_SCK, ADC input AIN4, and LVD monitor input LVD_IN2. |
| 19 | PD05 | bidirectional | GPIO PD05 with alternate functions LPUART1_TXD, ATIM3_CH0A and SPI_MISO, and ADC input AIN5. |
| 20 | PD06 | bidirectional | GPIO PD06 with alternate functions LPUART1_RXD, GTIM_ETR and SPI_MOSI, and ADC input AIN6. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-20-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 21 |

## CAD (KiCad official)

- Symbol: `HC32F002C4UB-ZFN20TR`
- Footprint: `Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm`
- 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `hc32f002c4ub-zfn20tr-etched.step` / `hc32f002c4ub-zfn20tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32f002c4ub-zfn20tr.step` / `hc32f002c4ub-zfn20tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XHSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589040661756850176) (415 pp, sha256 `a46a63adb2016518`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hc32f002c4ub-zfn20tr-datasheet.pdf)