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HC32D391FEUA-TFN32TR

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XHSC Microcontrollers (MCU/MPU/SOC), QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HC32D391FEUA-TFN32TR

XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(4x4)

HC32D391FEUA-TFN32TR from XHSC, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC14/XTAL32_OUT bidirectional GPIO PC14, also the 32.768 kHz low-speed oscillator output XTAL32_OUT and external interrupt EIRQ14; input voltage must not exceed 5 V when used as an input.
2 PC15/XTAL32_IN bidirectional GPIO PC15, also the 32.768 kHz low-speed oscillator input XTAL32_IN and external interrupt EIRQ15; input voltage must not exceed 5 V when used as an input.
3 PH0/XTAL_IN bidirectional GPIO PH0, also the high-speed crystal oscillator input XTAL_IN (4-24 MHz crystal, or 1-24 MHz external clock) and EIRQ0; input voltage must not exceed 5 V when used as an input.
4 PH1/XTAL_OUT bidirectional GPIO PH1, also the high-speed crystal oscillator output XTAL_OUT and external interrupt EIRQ1; input voltage must not exceed 5 V when used as an input.
5 NRST input Active-low reset pin; minimum reset pulse width is 500 ns, and it should be pulled up to VCC through a resistor when not used.
6 AVSS/VREFL power_in Analog ground and low reference voltage (AVSS = VSS); tie to VSS when the analog modules are not used.
7 AVCC/VREFH power_in Analog supply, same voltage as VCC (1.8-3.6 V), and ADC high reference VREFH which must not exceed AVCC; short to AVCC when the ADC is not used.
8 PA0/ADC1_IN0 bidirectional GPIO PA0, also ADC1 analog input ADC1_IN0, EIRQ0 and WKUP0_0; when used as analog input the voltage must not exceed VREFH/AVCC.
9 PA4/ADC1_IN4 bidirectional GPIO PA4, also ADC1 analog input ADC1_IN4 and EIRQ4; when used as analog input the voltage must not exceed VREFH/AVCC.
10 PB1/ADC1_IN9 bidirectional GPIO PB1, also ADC1 analog input ADC1_IN9 and EIRQ1/WKUP0_1; when used as analog input the voltage must not exceed VREFH/AVCC.
11 PB2/PVD2EXINP bidirectional GPIO PB2, also the PVD2 external comparison voltage input PVD2EXINP and EIRQ2/WKUP0_2; input voltage must not exceed 5 V when used as an input.
12 PB10 bidirectional GPIO PB10, also external interrupt EIRQ10; input voltage must not exceed 5 V when used as an input.
13 VCAP_1 power_out Core-voltage (main regulator) pin; connect a capacitor close to VSS of 0.047 µF, 0.1 µF or 0.22 µF with ESR < 0.3 Ω.
14 VSS power_in Ground, 0 V.
15 VCC power_in Main supply, 1.8 V to 3.6 V; decouple close to VSS with the capacitors given in the power-supply scheme.
16 PB12 bidirectional GPIO PB12, also external interrupt EIRQ12 and VCOUT1; input voltage must not exceed 5 V when used as an input.
17 PB13 bidirectional GPIO PB13, also external interrupt EIRQ13 and VCOUT2; input voltage must not exceed 5 V when used as an input.
18 PB14 bidirectional GPIO PB14, also external interrupt EIRQ14 and VCOUT3; input voltage must not exceed 5 V when used as an input.
19 PB15 bidirectional GPIO PB15, also external interrupt EIRQ15 and RTC_OUT (1 Hz clock output); input voltage must not exceed 5 V when used as an input.
20 PA8 bidirectional GPIO PA8, also external interrupt EIRQ8/WKUP2_0, MCO_1 clock output and USBFS_SOF; input voltage must not exceed 5 V when used as an input.
21 PA11/USBFS_DM bidirectional GPIO PA11, also the USB full-speed PHY D- signal USBFS_DM and EIRQ11/WKUP2_3; this pin is not 5 V tolerant, and its input voltage must not exceed VCC+0.3 V.
22 PA12/USBFS_DP bidirectional GPIO PA12, also the USB full-speed PHY D+ signal USBFS_DP and EIRQ12/WKUP3_0; this pin is not 5 V tolerant, and its input voltage must not exceed VCC+0.3 V.
23 PA13/JTMS_SWDIO bidirectional SWD data I/O JTMS_SWDIO, also GPIO PA13, EIRQ13 and WKUP3_1; input voltage must not exceed 5 V when used as an input.
24 VCC power_in Main supply, 1.8 V to 3.6 V; decouple close to VSS with the capacitors given in the power-supply scheme.
25 PA14/JTCK_SWCLK bidirectional SWD clock JTCK_SWCLK, also GPIO PA14, EIRQ14 and WKUP3_2; input voltage must not exceed 5 V when used as an input.
26 PA15/JTDI bidirectional JTAG data input JTDI, also GPIO PA15, EIRQ15 and WKUP3_3; input voltage must not exceed 5 V when used as an input.
27 PB3/JTDO_TRACESWO bidirectional JTAG data output / trace SWO JTDO_TRACESWO, also GPIO PB3 and EIRQ3/WKUP0_3; input voltage must not exceed 5 V when used as an input.
28 PB4/NJTRST bidirectional JTAG reset NJTRST (active low), also GPIO PB4 and EIRQ4/WKUP1_0; input voltage must not exceed 5 V when used as an input.
29 PB5 bidirectional GPIO PB5, also external interrupt EIRQ5/WKUP1_1 and I2S4_EXCK; input voltage must not exceed 5 V when used as an input.
30 PB11/MD input Input-only pin (NMI, mode input MD); it must be held high when NRST is released, and a 4.7 kΩ pull-up to VCC is recommended; 5 V tolerant.
31 PH2 bidirectional GPIO PH2, also external interrupt EIRQ2, FCM reference clock input FCMREF and I2S3_EXCK; input voltage must not exceed 5 V when used as an input.
32 PC13 bidirectional GPIO PC13, also external interrupt EIRQ13, RTC_OUT and I2S3_MCK; input voltage must not exceed 5 V when used as an input.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer XHSC
Package QFN-32-EP(4x4)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: HC32D391FEUA-TFN32TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: hc32d391feua-tfn32tr-etched.step / hc32d391feua-tfn32tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32d391feua-tfn32tr.step / hc32d391feua-tfn32tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (91 pp, sha256 8acad70cc52a1da9, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF