HC32A448JCTI-LQ48

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32A448JCTI-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PH2	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ2 external interrupt and FCMREF clock-frequency measurement reference input.
2	PC13	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ13 external interrupt and RTC_OUT 1Hz clock output.
3	PC14	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; when used as the sub-clock function it is the XTAL32_IN 32.768kHz oscillator input.
4	PC15	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; when used as the sub-clock function it is the XTAL32_OUT 32.768kHz oscillator output.
5	PH0	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also the XTAL_IN main crystal oscillator interface (4-25MHz) and EIRQ0 external interrupt.
6	PH1	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also the XTAL_EXT/XTAL_OUT main oscillator output and EIRQ1 external interrupt.
7	NRST	input	Reset terminal, active low; connect to VCC (pull-up) when not in use.
8	AVSS/VREFL	power_in	Analog power ground, connected to the same voltage as VSS; short to VSS when the analog module is not used; also the ADC/DAC reference low voltage VREFL.
9	AVCC/VREFH	power_in	Analog power supply, connected to the same voltage as VCC (1.8V-3.6V); short to VCC when the analog module is not used; also the analog reference high voltage VREFH.
10	PA0	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN0 and CMP1_INP1 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ0/WKUP0_0 wake-up.
11	PA1	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN1 and CMP1_INP2 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ1 external interrupt.
12	PA2	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN2 and CMP1_INP3 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ2/WKUP2 wake-up.
13	PA3	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN3, CMP1_INP4 and CMP2_INP4 analog inputs (analog voltage must not exceed AVCC/VREFH) and EIRQ3 external interrupt.
14	PA4	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC12_IN4, CMP2_INP1, CMP3_INP4 analog inputs and DAC_OUT1 analog output (analog voltage must not exceed AVCC/VREFH).
15	PA5	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC12_IN5, CMP2_INP2 analog inputs and DAC_OUT2 analog output (analog voltage must not exceed AVCC/VREFH).
16	PA6	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN6 and CMP2_INP3 analog inputs (analog voltage must not exceed AVCC/VREFH).
17	PA7	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive; NOT 5V-tolerant, so input voltage must not exceed VCC; also ADC123_IN7 and CMP1234_INM1 analog inputs.
18	PB0	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN8 and CMP3_INP1 analog inputs (analog voltage must not exceed AVCC/VREFH) and EIRQ0 external interrupt.
19	PB1	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN9, CMP3_INP2 and CMP4_INP2 analog inputs and EIRQ1/WKUP0_1 wake-up.
20	PB2	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also PVD2EXINP external PVD2 comparison input and EIRQ2/WKUP0_2 wake-up.
21	PB10	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC3_IN11 analog input (analog voltage must not exceed AVCC/VREFH) and ADTRG2 ADC external start source.
22	VCAP_1	power_out	Core voltage pin; connect a 0.1µF or 0.22µF capacitor to the nearby VSS pin to stabilize the core voltage.
23	VSS	power_in	Source ground, connected to 0V.
24	VCC	power_in	Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin.
25	PB12	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ12 external interrupt and VCOUT1 CMP1 comparator output.
26	PB13	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ13 external interrupt and VCOUT2 CMP2 comparator output.
27	PB14	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ14 external interrupt and VCOUT3 CMP3 comparator output.
28	PB15	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ15 external interrupt and the RTC_OUT 1Hz clock output.
29	PA8	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive; NOT 5V-tolerant, so input voltage must not exceed VCC; also CMP4_INM2 analog input, MCO_1 clock output and EIRQ8/WKUP2_0 wake-up.
30	PA9	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also CMP4_INP1 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ9/WKUP2_1 wake-up.
31	PA10	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also CMP4_INP4 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ10/WKUP2_2 wake-up.
32	PA11	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ11 external interrupt and WKUP2_3 wake-up.
33	PA12	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ12 external interrupt and WKUP3_0 wake-up.
34	PA13	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTMS_SWDIO serial-wire debug data input/output, EIRQ13 and WKUP3_1 wake-up.
35	VSS	power_in	Source ground, connected to 0V.
36	VCC	power_in	Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin.
37	PA14	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTCK_SWCLK serial-wire debug clock, EIRQ14 and WKUP3_2 wake-up.
38	PA15	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTDI JTAG data input, EIRQ15 and WKUP3_3 wake-up.
39	PB3	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTDO_TRACESWO debug output, EIRQ3 and WKUP0_3 wake-up.
40	PB4	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also NJTRST JTAG reset input, EIRQ4 and WKUP1_0 wake-up.
41	PB5	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG3 ADC external start source, EIRQ5 and WKUP1_1 wake-up.
42	PB6	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG2 ADC external start source, EIRQ6 and WKUP1_2 wake-up.
43	PB7	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG1 ADC external start source, EIRQ7 and WKUP1_3 wake-up.
44	PB11/MD	input	Mode terminal MD, which must be held low when NRST is released (low to high); a 4.7kΩ pull-down to VSS is recommended; the pin is also GPIO PB11 with EVNTP211 event port.
45	PB8	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ8 external interrupt, KEYOUT7 keyscan output and EXMC_WE external memory write enable.
46	PB9	bidirectional	General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ9 external interrupt, EMB_IN4 and EXMC_OE external memory output enable.
47	VSS	power_in	Source ground, connected to 0V.
48	VCC	power_in	Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin.

Key specifications

Parameter	Value
Manufacturer	XHSC
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC-VSS External main supply voltage (including AVCC, VCC)	VCC-VSS	-0.3		4	V		47
Input voltage on pins other than PA7,PA8,PC3~PC5	VIN			5.8	V	Printed VSS-0.3 to VCC+4.0 (maximum 5.8V)	47
Input voltage on pins PA7,PA8,PC3~PC5	VIN			4	V	Printed VSS-0.3 to VCC+0.7 (maximum 4.0V)	47
Voltage difference between different ground pins	/VSSx-VSS/			50	mV		47
Total current flowing into all VCCX power lines (source current)	∑IVCC			240	mA		47
Total current flowing (sinking) out of all VSSX ground wires	∑IVSS			-240	mA		47
Maximum current into each VCCX supply line (source current)	IVCC			100	mA		47
Maximum current out of each VSSX ground line (sink)	IVSS			-100	mA		47
Output current sink for any I/O and control pin	IIO			20	mA		47
Output current source for any I/O and control pin	IIO			-20	mA		47
Total output current on all I/O and control pins (48-pin package)	∑IIO	-80		80	mA	48-pin packages (note 2): ±80mA	47
Storage temperature range	TSTG	-65		150	°C		47
Junction temperature range (absolute maximum table)	TJ	-40		125	°C		47
Internal AHB clock frequency, high speed mode	fHCLK			200	MHz	High speed mode; PWRC2.DVS=0b11; PWRC3.DDAS=0xF	48
Internal AHB clock frequency, super low speed mode	fHCLK			8	MHz	Super low speed mode; PWRC2.DVS=0b10; PWRC3.DDAS=0x0	48
Standard operating voltage	VCC	1.8		3.6	V		48
Analog working voltage	VAVCC	1.8		3.6	V		48
Input voltage on 5V tolerant pin	VIN	-0.3		5.5	V	5V tolerant pin; 2V≤VCC≤3.6V; 2V≤VAVCC≤3.6V	48
Input voltage on 5V tolerant pin (low supply)	VIN	-0.3		5.2	V	5V tolerant pin; VCC<2V; VAVCC<2V	48
Input voltage on non-5V tolerant pin (PA7, PA8, PC3~PC5)	VIN	-0.3			V	Printed max Vcc+0.3	48
Junction temperature range (operating)	TJ	-40		125	°C		48
Operating temperature range	TA	-40		105	°C		48
VCC rise time rate	tVCC	20		20000	µs/V		48
VCC down time rate	tVCC	20		20000	µs/V		48
Thermal resistance junction-ambient tolerance (LQFP48)	θJA	-10		10	%	LQFP48 771.4 e=0.5	96
Thermal resistance junction-ambient (LQFP48)	θJA		75		℃/W	LQFP48 771.4 e=0.5	96
BOR monitoring voltage	VBOR	1.7	1.9	2.1	V	ICG1.BOR_LEV[1:0]=0b00	49
BOR monitoring voltage	VBOR	1.8	2	2.2	V	ICG1.BOR_LEV[1:0]=0b01	49
BOR monitoring voltage	VBOR	1.9	2.1	2.3	V	ICG1.BOR_LEV[1:0]=0b10	49
BOR monitoring voltage	VBOR	2.1	2.3	2.5	V	ICG1.BOR_LEV[1:0]=0b11	49
Power-on reset threshold, rising edge	VPOR	1.56	1.68	1.8	V	Rising edge	49
Power-on reset threshold, falling edge	VPDR	1.52	1.64	1.76	V	Falling edge	49
Inrush current at regulator power-up (POR or wake-up from standby)	IRUSH		100	150	mA		49
NRST reset minimum width	TNRST	10			μs		49
Power-on reset release time	TRSTPOR		2500	3000	μs		50
PVD1 monitoring voltage	VPVD1	1.8	2	2.2	V	PVD1LVL[2:0]=0b000	49
PVD1 monitoring voltage	VPVD1	1.9	2.1	2.3	V	PVD1LVL[2:0]=0b001	49
PVD1 monitoring voltage	VPVD1	2.1	2.3	2.5	V	PVD1LVL[2:0]=0b010	49
PVD1 monitoring voltage	VPVD1	2.33	2.55	2.77	V	PVD1LVL[2:0]=0b011	49
PVD1 monitoring voltage	VPVD1	2.43	2.65	2.87	V	PVD1LVL[2:0]=0b100	49
PVD1 monitoring voltage	VPVD1	2.53	2.75	2.97	V	PVD1LVL[2:0]=0b101	49
PVD1 monitoring voltage	VPVD1	2.63	2.85	3.07	V	PVD1LVL[2:0]=0b110	49
PVD1 monitoring voltage	VPVD1	2.73	2.95	3.17	V	PVD1LVL[2:0]=0b111	49
NRST reset release time	TINRST	25	35	50	μs		49
BOR reset release time	TRSTBOR	440	520	610	μs		49
Supply current RUN, while(1), full module clock OFF	ICC_RUN			29	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current RUN, while(1), full module clock ON	ICC_RUN			43	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current DHRYSTONE, cache OFF	ICC_DHRYSTONE			30	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current DHRYSTONE, cache ON	ICC_DHRYSTONE			30	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current SLEEP, full module clock OFF	ICC_SLEEP			20	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current SLEEP, full module clock ON	ICC_SLEEP			34	mA	High speed mode fHCLK=200MHz; TA=85°C	51
Supply current RUN, while(1), all module clock OFF	ICC_RUN			33	mA	High speed mode fHCLK=200MHz; TA=105°C	51
Supply current RUN, while(1), all module clock ON	ICC_RUN			48	mA	High speed mode fHCLK=200MHz; TA=105°C	51
Supply current DHRYSTONE, cache OFF	ICC_DHRYSTONE			34	mA	High speed mode fHCLK=200MHz; TA=105°C	51
Supply current DHRYSTONE, cache ON	ICC_DHRYSTONE			34	mA	High speed mode fHCLK=200MHz; TA=105°C	51
Supply current SLEEP, all module clock OFF	ICC_SLEEP			24	mA	High speed mode fHCLK=200MHz; TA=105°C	51
Supply current SLEEP, all module clock ON	ICC_SLEEP			39	mA	High speed mode fHCLK=200MHz; TA=105°C	51

CAD (KiCad official)

Symbol: HC32A448JCTI-LQ48
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: hc32a448jcti-lq48-etched.step / hc32a448jcti-lq48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32a448jcti-lq48.step / hc32a448jcti-lq48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XHSC datasheet (99 pp, sha256 2b71e9fa5e308157, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# HC32A448JCTI-LQ48

**XHSC** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

HC32A448JCTI-LQ48 from XHSC, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ2 external interrupt and FCMREF clock-frequency measurement reference input. |
| 2 | PC13 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ13 external interrupt and RTC_OUT 1Hz clock output. |
| 3 | PC14 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; when used as the sub-clock function it is the XTAL32_IN 32.768kHz oscillator input. |
| 4 | PC15 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; when used as the sub-clock function it is the XTAL32_OUT 32.768kHz oscillator output. |
| 5 | PH0 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also the XTAL_IN main crystal oscillator interface (4-25MHz) and EIRQ0 external interrupt. |
| 6 | PH1 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also the XTAL_EXT/XTAL_OUT main oscillator output and EIRQ1 external interrupt. |
| 7 | NRST | input | Reset terminal, active low; connect to VCC (pull-up) when not in use. |
| 8 | AVSS/VREFL | power_in | Analog power ground, connected to the same voltage as VSS; short to VSS when the analog module is not used; also the ADC/DAC reference low voltage VREFL. |
| 9 | AVCC/VREFH | power_in | Analog power supply, connected to the same voltage as VCC (1.8V-3.6V); short to VCC when the analog module is not used; also the analog reference high voltage VREFH. |
| 10 | PA0 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN0 and CMP1_INP1 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ0/WKUP0_0 wake-up. |
| 11 | PA1 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN1 and CMP1_INP2 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ1 external interrupt. |
| 12 | PA2 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN2 and CMP1_INP3 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ2/WKUP2 wake-up. |
| 13 | PA3 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC1_IN3, CMP1_INP4 and CMP2_INP4 analog inputs (analog voltage must not exceed AVCC/VREFH) and EIRQ3 external interrupt. |
| 14 | PA4 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC12_IN4, CMP2_INP1, CMP3_INP4 analog inputs and DAC_OUT1 analog output (analog voltage must not exceed AVCC/VREFH). |
| 15 | PA5 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC12_IN5, CMP2_INP2 analog inputs and DAC_OUT2 analog output (analog voltage must not exceed AVCC/VREFH). |
| 16 | PA6 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN6 and CMP2_INP3 analog inputs (analog voltage must not exceed AVCC/VREFH). |
| 17 | PA7 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive; NOT 5V-tolerant, so input voltage must not exceed VCC; also ADC123_IN7 and CMP1234_INM1 analog inputs. |
| 18 | PB0 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN8 and CMP3_INP1 analog inputs (analog voltage must not exceed AVCC/VREFH) and EIRQ0 external interrupt. |
| 19 | PB1 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC123_IN9, CMP3_INP2 and CMP4_INP2 analog inputs and EIRQ1/WKUP0_1 wake-up. |
| 20 | PB2 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also PVD2EXINP external PVD2 comparison input and EIRQ2/WKUP0_2 wake-up. |
| 21 | PB10 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADC3_IN11 analog input (analog voltage must not exceed AVCC/VREFH) and ADTRG2 ADC external start source. |
| 22 | VCAP_1 | power_out | Core voltage pin; connect a 0.1µF or 0.22µF capacitor to the nearby VSS pin to stabilize the core voltage. |
| 23 | VSS | power_in | Source ground, connected to 0V. |
| 24 | VCC | power_in | Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin. |
| 25 | PB12 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ12 external interrupt and VCOUT1 CMP1 comparator output. |
| 26 | PB13 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ13 external interrupt and VCOUT2 CMP2 comparator output. |
| 27 | PB14 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ14 external interrupt and VCOUT3 CMP3 comparator output. |
| 28 | PB15 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ15 external interrupt and the RTC_OUT 1Hz clock output. |
| 29 | PA8 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive; NOT 5V-tolerant, so input voltage must not exceed VCC; also CMP4_INM2 analog input, MCO_1 clock output and EIRQ8/WKUP2_0 wake-up. |
| 30 | PA9 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also CMP4_INP1 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ9/WKUP2_1 wake-up. |
| 31 | PA10 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also CMP4_INP4 analog input (analog voltage must not exceed AVCC/VREFH) and EIRQ10/WKUP2_2 wake-up. |
| 32 | PA11 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ11 external interrupt and WKUP2_3 wake-up. |
| 33 | PA12 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ12 external interrupt and WKUP3_0 wake-up. |
| 34 | PA13 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTMS_SWDIO serial-wire debug data input/output, EIRQ13 and WKUP3_1 wake-up. |
| 35 | VSS | power_in | Source ground, connected to 0V. |
| 36 | VCC | power_in | Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin. |
| 37 | PA14 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTCK_SWCLK serial-wire debug clock, EIRQ14 and WKUP3_2 wake-up. |
| 38 | PA15 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTDI JTAG data input, EIRQ15 and WKUP3_3 wake-up. |
| 39 | PB3 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also JTDO_TRACESWO debug output, EIRQ3 and WKUP0_3 wake-up. |
| 40 | PB4 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also NJTRST JTAG reset input, EIRQ4 and WKUP1_0 wake-up. |
| 41 | PB5 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG3 ADC external start source, EIRQ5 and WKUP1_1 wake-up. |
| 42 | PB6 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG2 ADC external start source, EIRQ6 and WKUP1_2 wake-up. |
| 43 | PB7 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also ADTRG1 ADC external start source, EIRQ7 and WKUP1_3 wake-up. |
| 44 | PB11/MD | input | Mode terminal MD, which must be held low when NRST is released (low to high); a 4.7kΩ pull-down to VSS is recommended; the pin is also GPIO PB11 with EVNTP211 event port. |
| 45 | PB8 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ8 external interrupt, KEYOUT7 keyscan output and EXMC_WE external memory write enable. |
| 46 | PB9 | bidirectional | General-purpose I/O with pull-up/pull-down, open-drain and Low/Medium/High drive, 5V-tolerant; also EIRQ9 external interrupt, EMB_IN4 and EXMC_OE external memory output enable. |
| 47 | VSS | power_in | Source ground, connected to 0V. |
| 48 | VCC | power_in | Power supply, connected to 1.8V-3.6V, with a decoupling capacitor to the nearby VSS pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC-VSS External main supply voltage (including AVCC, VCC) | VCC-VSS | -0.3 |  | 4 | V |  | 47 |
| Input voltage on pins other than PA7,PA8,PC3~PC5 | VIN |  |  | 5.8 | V | Printed VSS-0.3 to VCC+4.0 (maximum 5.8V) | 47 |
| Input voltage on pins PA7,PA8,PC3~PC5 | VIN |  |  | 4 | V | Printed VSS-0.3 to VCC+0.7 (maximum 4.0V) | 47 |
| Voltage difference between different ground pins | /VSSx-VSS/ |  |  | 50 | mV |  | 47 |
| Total current flowing into all VCCX power lines (source current) | ∑IVCC |  |  | 240 | mA |  | 47 |
| Total current flowing (sinking) out of all VSSX ground wires | ∑IVSS |  |  | -240 | mA |  | 47 |
| Maximum current into each VCCX supply line (source current) | IVCC |  |  | 100 | mA |  | 47 |
| Maximum current out of each VSSX ground line (sink) | IVSS |  |  | -100 | mA |  | 47 |
| Output current sink for any I/O and control pin | IIO |  |  | 20 | mA |  | 47 |
| Output current source for any I/O and control pin | IIO |  |  | -20 | mA |  | 47 |
| Total output current on all I/O and control pins (48-pin package) | ∑IIO | -80 |  | 80 | mA | 48-pin packages (note 2): ±80mA | 47 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 47 |
| Junction temperature range (absolute maximum table) | TJ | -40 |  | 125 | °C |  | 47 |
| Internal AHB clock frequency, high speed mode | fHCLK |  |  | 200 | MHz | High speed mode; PWRC2.DVS=0b11; PWRC3.DDAS=0xF | 48 |
| Internal AHB clock frequency, super low speed mode | fHCLK |  |  | 8 | MHz | Super low speed mode; PWRC2.DVS=0b10; PWRC3.DDAS=0x0 | 48 |
| Standard operating voltage | VCC | 1.8 |  | 3.6 | V |  | 48 |
| Analog working voltage | VAVCC | 1.8 |  | 3.6 | V |  | 48 |
| Input voltage on 5V tolerant pin | VIN | -0.3 |  | 5.5 | V | 5V tolerant pin; 2V≤VCC≤3.6V; 2V≤VAVCC≤3.6V | 48 |
| Input voltage on 5V tolerant pin (low supply) | VIN | -0.3 |  | 5.2 | V | 5V tolerant pin; VCC<2V; VAVCC<2V | 48 |
| Input voltage on non-5V tolerant pin (PA7, PA8, PC3~PC5) | VIN | -0.3 |  |  | V | Printed max Vcc+0.3 | 48 |
| Junction temperature range (operating) | TJ | -40 |  | 125 | °C |  | 48 |
| Operating temperature range | TA | -40 |  | 105 | °C |  | 48 |
| VCC rise time rate | tVCC | 20 |  | 20000 | µs/V |  | 48 |
| VCC down time rate | tVCC | 20 |  | 20000 | µs/V |  | 48 |
| Thermal resistance junction-ambient tolerance (LQFP48) | θJA | -10 |  | 10 | % | LQFP48 7*7*1.4 e=0.5 | 96 |
| Thermal resistance junction-ambient (LQFP48) | θJA |  | 75 |  | ℃/W | LQFP48 7*7*1.4 e=0.5 | 96 |
| BOR monitoring voltage | VBOR | 1.7 | 1.9 | 2.1 | V | ICG1.BOR_LEV[1:0]=0b00 | 49 |
| BOR monitoring voltage | VBOR | 1.8 | 2 | 2.2 | V | ICG1.BOR_LEV[1:0]=0b01 | 49 |
| BOR monitoring voltage | VBOR | 1.9 | 2.1 | 2.3 | V | ICG1.BOR_LEV[1:0]=0b10 | 49 |
| BOR monitoring voltage | VBOR | 2.1 | 2.3 | 2.5 | V | ICG1.BOR_LEV[1:0]=0b11 | 49 |
| Power-on reset threshold, rising edge | VPOR | 1.56 | 1.68 | 1.8 | V | Rising edge | 49 |
| Power-on reset threshold, falling edge | VPDR | 1.52 | 1.64 | 1.76 | V | Falling edge | 49 |
| Inrush current at regulator power-up (POR or wake-up from standby) | IRUSH |  | 100 | 150 | mA |  | 49 |
| NRST reset minimum width | TNRST | 10 |  |  | μs |  | 49 |
| Power-on reset release time | TRSTPOR |  | 2500 | 3000 | μs |  | 50 |
| PVD1 monitoring voltage | VPVD1 | 1.8 | 2 | 2.2 | V | PVD1LVL[2:0]=0b000 | 49 |
| PVD1 monitoring voltage | VPVD1 | 1.9 | 2.1 | 2.3 | V | PVD1LVL[2:0]=0b001 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.1 | 2.3 | 2.5 | V | PVD1LVL[2:0]=0b010 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.33 | 2.55 | 2.77 | V | PVD1LVL[2:0]=0b011 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.43 | 2.65 | 2.87 | V | PVD1LVL[2:0]=0b100 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.53 | 2.75 | 2.97 | V | PVD1LVL[2:0]=0b101 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.63 | 2.85 | 3.07 | V | PVD1LVL[2:0]=0b110 | 49 |
| PVD1 monitoring voltage | VPVD1 | 2.73 | 2.95 | 3.17 | V | PVD1LVL[2:0]=0b111 | 49 |
| NRST reset release time | TINRST | 25 | 35 | 50 | μs |  | 49 |
| BOR reset release time | TRSTBOR | 440 | 520 | 610 | μs |  | 49 |
| Supply current RUN, while(1), full module clock OFF | ICC_RUN |  |  | 29 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current RUN, while(1), full module clock ON | ICC_RUN |  |  | 43 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current DHRYSTONE, cache OFF | ICC_DHRYSTONE |  |  | 30 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current DHRYSTONE, cache ON | ICC_DHRYSTONE |  |  | 30 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current SLEEP, full module clock OFF | ICC_SLEEP |  |  | 20 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current SLEEP, full module clock ON | ICC_SLEEP |  |  | 34 | mA | High speed mode fHCLK=200MHz; TA=85°C | 51 |
| Supply current RUN, while(1), all module clock OFF | ICC_RUN |  |  | 33 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |
| Supply current RUN, while(1), all module clock ON | ICC_RUN |  |  | 48 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |
| Supply current DHRYSTONE, cache OFF | ICC_DHRYSTONE |  |  | 34 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |
| Supply current DHRYSTONE, cache ON | ICC_DHRYSTONE |  |  | 34 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |
| Supply current SLEEP, all module clock OFF | ICC_SLEEP |  |  | 24 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |
| Supply current SLEEP, all module clock ON | ICC_SLEEP |  |  | 39 | mA | High speed mode fHCLK=200MHz; TA=105°C | 51 |

## CAD (KiCad official)

- Symbol: `HC32A448JCTI-LQ48`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `hc32a448jcti-lq48-etched.step` / `hc32a448jcti-lq48-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hc32a448jcti-lq48.step` / `hc32a448jcti-lq48.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XHSC datasheet](docs/hc32a448jcti-lq48-datasheet.pdf) (99 pp, sha256 `2b71e9fa5e308157`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hc32a448jcti-lq48-datasheet.pdf)