component
HA9P5002-5Z
Public Made by Adomby adom
RENESAS Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownHA9P5002-5Z
RENESAS · Pre-ordered Chips · SOIC-8
HA9P5002-5Z from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Buffer output, capable of 200mA continuous (400mA pulsed, 50ms on/1s off) with about 3 ohm typical output resistance. |
| 2 | V2+ | power_in | Positive supply terminal of the output stage; total V+ to V- supply must not exceed 44V and should be bypassed with 0.01 to 0.1uF ceramic capacitors close to the pin. |
| 3 | NC | unconnected | No internal connection. |
| 4 | V1- | power_in | Negative supply terminal of the input stage (also the die substrate potential); input voltage is limited to the range V1+ to V1-. |
| 5 | IN | input | Buffer input with typically 3 Mohm input resistance (1.5 Mohm min), driven through a 50 ohm to 1k series source resistance for stability with small capacitive loads. |
| 6 | NC | unconnected | No internal connection. |
| 7 | V2- | power_in | Negative supply terminal of the output stage; total V+ to V- supply must not exceed 44V and should be bypassed with 0.01 to 0.1uF ceramic capacitors close to the pin. |
| 8 | V1+ | power_in | Positive supply terminal of the input stage; input voltage is limited to the range V1+ to V1-. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Offset Voltage | 5 | 20 | mV | 25°C | 3 | ||
| Offset Voltage | 10 | 30 | mV | Full temp | 3 | ||
| Bias Current | 2 | 7 | µA | 25°C | 3 | ||
| Bias Current | 2.4 | 10 | µA | Full temp | 3 | ||
| Input Resistance | 1.5 | 3 | MΩ | Full temp | 3 | ||
| Voltage Gain | 0.98 | V/V | VOUT = 10V, RL = 1k, Full temp | 3 | |||
| Output Voltage Swing | 10 | 11.2 | V | RL = 100Ω, 25°C | 3 | ||
| Output Voltage Swing | 10 | 13.9 | V | RL = 1k, VS = 15V, Full temp | 3 | ||
| Output Voltage Swing | 10 | 10.5 | V | RL = 1k, VS = 12V, Full temp | 3 | ||
| Output Resistance | 3 | 10 | Ω | Full temp | 3 | ||
| Slew Rate | 1 | 1.3 | V/ns | 25°C | 3 | ||
| Supply Current | 10 | mA | Full temp | 4 | |||
| Power Supply Rejection Ratio | 54 | 64 | dB | AV = 10V, Full temp | 4 | ||
| Supply Current | 8.3 | mA | 25°C | 4 | |||
| Average Offset Voltage Drift | 30 | µV/°C | Full temp | 3 | |||
| Input Noise Voltage | 18 | µVP-P | 10Hz-1MHz, 25°C | 3 | |||
| Voltage Gain | 0.995 | V/V | VOUT = 10V, RL = 1k, 25°C | 3 | |||
| -3dB Bandwidth | 110 | MHz | VIN = 1VP-P, 25°C | 3 | |||
| Output Current | 220 | mA | VIN = 10V, RL = 40Ω, 25°C | 3 | |||
| Settling Time | 50 | ns | To 0.1%, 25°C | 3 | |||
| Voltage Between V+ and V- Terminals | 44 | V | 3 | ||||
| Output Current (Continuous) | 200 | mA | 3 | ||||
| Output Current (Pulsed) | 400 | mA | 50ms On, 1s Off | 3 | |||
| Max Junction Temperature (Plastic Packages) | 150 | °C | Note 2 | 3 | |||
| Max Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Max Lead Temperature (Soldering 10s) | 300 | °C | PLCC and SOIC - Lead Tips Only | 3 | |||
| Operating Temperature Range | 0 | 75 | °C | HA-5002-5 | 3 | ||
| Thermal Resistance Junction to Ambient | θJA | 157 | °C/W | SOIC Package, Note 3 | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | can packages, and below +150°C for the plastic packages. 3. For JA is measured with the component mounted on an evaluation PC board in free air. | 3 |
CAD (KiCad official)
- Symbol:
HA9P5002-5Z - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ha9p5002-5z-etched.step/ha9p5002-5z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ha9p5002-5z.step/ha9p5002-5z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (12 pp, sha256
ec23a77028608eb8, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).