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Set visibility: public

Ray ·3376ee5133 ·1mo ago ·parent ae6d2e6
1 file changed +8−5
page.json+8−5
@@ -32,7 +32,7 @@         "number": "1",         "name": "OUTA",         "type": "output",-        "description": "Amplifier A output. Rail-to-rail CMOS output, typically swings to within 30mV (RL>1k\u03a9) or 120mV (RL=150\u03a9) of either supply rail; ~120mA min output current capability."+        "description": "Amplifier A output. Rail-to-rail CMOS output, typically swings to within 30mV (RL>1kΩ) or 120mV (RL=150Ω) of either supply rail; ~120mA min output current capability."       },       {         "number": "2",@@ -50,7 +50,7 @@         "number": "4",         "name": "VSS",         "type": "power_in",-        "description": "Negative supply / ground. For single-supply operation tie to GND; for dual-supply operation connect to the negative rail (typ. -1.25V to -2.75V). Bypass with a 0.1\u00b5F ceramic capacitor to ground."+        "description": "Negative supply / ground. For single-supply operation tie to GND; for dual-supply operation connect to the negative rail (typ. -1.25V to -2.75V). Bypass with a 0.1µF ceramic capacitor to ground."       },       {         "number": "5",@@ -68,13 +68,13 @@         "number": "7",         "name": "OUTB",         "type": "output",-        "description": "Amplifier B output. Rail-to-rail CMOS output, typically swings to within 30mV (RL>1k\u03a9) or 120mV (RL=150\u03a9) of either supply rail; ~120mA min output current capability."+        "description": "Amplifier B output. Rail-to-rail CMOS output, typically swings to within 30mV (RL>1kΩ) or 120mV (RL=150Ω) of either supply rail; ~120mA min output current capability."       },       {         "number": "8",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply. Single-supply operating range 2.5V to 5.5V (absolute max 7.5V VDD-VSS). Bypass with a 0.1\u00b5F ceramic capacitor to VSS placed close to the pin."+        "description": "Positive supply. Single-supply operating range 2.5V to 5.5V (absolute max 7.5V VDD-VSS). Bypass with a 0.1µF ceramic capacitor to VSS placed close to the pin."       }     ],     "provenance": {@@ -138,5 +138,8 @@     "docs/gs8092-sr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file