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GP9105-F50-N-SW

Public Made by Adom

by adom

Guestgood Analog To Digital Converters (ADC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GP9105-F50-N-SW

Guestgood · Analog To Digital Converters (ADC) · SOP-8

GP9105-F50-N-SW from Guestgood, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; leave unconnected.
2 NC unconnected No connect; leave unconnected.
3 VIN power_in Analog voltage input, range 0 V to VCC (absolute maximum -0.3 V to VCC + 0.3 V), converted to PWM duty cycle DPWM = VIN/VCC.
4 NC unconnected No connect; leave unconnected.
5 GND power_in Ground.
6 PWM output PWM duty-cycle output, 0% to 100% duty, frequency 1 Hz to 1 MHz (default 1 kHz).
7 PWMB output Complementary signal of the PWM output.
8 VCC power_in Power supply, 2.7 V to 5.5 V (typical 5 V); the SW ordering options list 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Guestgood
Package SOP-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.7 5 5.5 V 6
Supply voltage (ordering variant -SW) VCC 4.5 5.5 V Ordering table, GP9105-F*-N-SW 8
Operating temperature (ordering variant -SW) -40 85 °C Ordering table, GP9105-F*-N-SW 8
PWM frequency error ∆fpwm -3 0 3 % 6
PWM duty cycle range Dpwm 0 100 % Average duty cycle (note 2) 6
PWM duty cycle error ∆Dpwm 0.5 1 % 6
PWM jitter Jpwm 0.1 0.2 %p-p Measured at 1 kHz (note 3) 6
Supply current ICC 2 5 mA VCC @ 5.0V 6
Input voltage VIN 0 V Max printed as VCC (expression, not converted) 6
Input leakage current IIL 3 μA VIN = VCC or VSS 6
Output leakage current ILO 3 μA VIN = VCC or VSS 6
Output low voltage VOL 0.4 V VCC @ 5.0V, IOL = 10 mA 6
Output high voltage VOH 0.4 V VCC @ 5.0V, IOL = 10 mA; printed as VCC-0.4 V, so the value 0.4 is the offset below VCC (not computed) 6
Output rise time Tr 20 40 ns VCC @ 5.0V, CLOAD=5pF 6
Output fall time Tf 20 40 ns VCC @ 5.0V, CLOAD=5pF 6
Industrial operating temperature -40 125 °C 2
Storage temperature -50 125 °C 2
Input voltage range (absolute) VIN -0.3 V Max printed as VCC + 0.3 V (expression, not converted) 2
Maximum voltage 8 V 2
ESD protection 4000 V Printed as > 4000 V; test model not stated 2

CAD (KiCad official)

  • Symbol: GP9105-F50-N-SW
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: gp9105-f50-n-sw-etched.step / gp9105-f50-n-sw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gp9105-f50-n-sw.step / gp9105-f50-n-sw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Guestgood datasheet (9 pp, sha256 93fa6e97af1a26b9, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF