component

GP9101-F500-N-SW

Public Made by Adom

by adom

Guestgood Analog To Digital Converters (ADCs), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiongp9101-f500-n-swfactory-2.0.0extractor-text

Verified GP9101-F500-N-SW

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: GP9101-F500-N-SW · SOP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 9-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sboxfu26/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.9)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ gp9101-f500-n-sw.kicad_sym✓ gp9101-f500-n-sw.kicad_mod✓ gp9101-f500-n-sw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers gp9101-f500-n-sw: viewers · Ray 1d ago
gp9101-f500-n-sw-etched.glb Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw-etched.step gp9101-f500-n-sw: factory component page (tier=lcsc) · Ray 1d ago
gp9101-f500-n-sw-hero.glb gp9101-f500-n-sw: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
gp9101-f500-n-sw-hero.overlay.json Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw.glb Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw.kicad_mod Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw.kicad_sym Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw.lbr Publish 0.1.0 · Ray 1d ago
gp9101-f500-n-sw.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 1d ago

GP9101-F500-N-SW

Guestgood · Analog To Digital Converters (ADCs) · SOP-8

GP9101-F500-N-SW from Guestgood, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin, left unconnected.
2 NC unconnected No connect pin, left unconnected.
3 VIN power_in Analog voltage input from 0 V to VCC (absolute maximum -0.3 V to VCC + 0.3 V), converted to PWM duty cycle DPWM = VIN/VCC.
4 NC unconnected No connect pin, left unconnected.
5 GND power_in Ground.
6 PWM output PWM duty-cycle output, 0% to 100% duty at 1 Hz to 1 MHz (default 1 kHz), VOL max 0.4 V at 10 mA.
7 PWMB output Complementary signal of the PWM output.
8 VCC power_in Power supply, 4.5 V to 5.5 V (5 V typical).

Key specifications

Parameter Value
Manufacturer Guestgood
Package SOP-8
Category ADC/DAC/Data Conversion
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC VCC 4.5 5 5.5 V 6
PWM signal frequency fpwm 1 Hz 6
PWM signal frequency error ∆fpwm -3 0 3 % 6
PWM duty cycle error ∆Dpwm 0.5 1 % 6
PWM duty cycle Dpwm 0 100 % 6
PWM signal jitter Jpwm 0.1 0.2 %p-p 6
Supply power consumption (supply current) ICC 2 2.5 mA VCC @ 5.0V 6
Input voltage VIN 0 V 6
Input leakage current IIL 3 μA VIN = VCC or VSS 6
Output leakage current ILO 3 μA VIN = VCC or VSS 6
Output low voltage VOL 0.4 V VCC @ 5.0V, IOL = 10 mA 6
Output rise time Tr 20 40 ns VCC @ 5.0V, CLOAD=5pF 6
Output fall time Tf 20 40 ns VCC @ 5.0V, CLOAD=5pF 6
Industrial operating temperature -40 125 ℃ 2
Storage temperature -50 125 ℃ 2
Input voltage (absolute maximum) -0.3 V Upper limit printed as VCC + 0.3 V 2
Maximum voltage 5.5 V 2
ESD protection 4000 V Printed as > 4000 V; ESD model not stated 2
Operating temperature (SW variant) -40 85 ℃ Ordering row GP9101-F*-N-SW, package SOP8 8

CAD (KiCad official)

  • Symbol: GP9101-F500-N-SW
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: gp9101-f500-n-sw-etched.step / gp9101-f500-n-sw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gp9101-f500-n-sw.step / gp9101-f500-n-sw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Guestgood datasheet (9 pp, sha256 daa0762d946d057b, retrieved 2026-11-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF