component
GP8521J
Public Made by Adomby adom
HaloChip AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownGP8521J
HaloChip · AC-DC Controllers And Regulators · SOP-8
GP8521J from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground pin, the IC ground reference (芯片的地); the datasheet gives no electrical limit for this pin. |
| 2 | VDD | power_in | Chip power supply pin with an absolute maximum of 35 V, a UVLO threshold of 7.5 V typical, and a VDD OVP threshold of 38.5 V typical. |
| 3 | FB | input | Output voltage feedback input with an absolute range of -0.3 to 7 V, an open-loop voltage of 5.3 V typical, and an OLP power-limit threshold of 3.6 V. |
| 4 | CS | input | Current sense pin, with the sense resistor connected between CS and GND, an absolute range of -0.3 to 7 V, and an internal current-limit threshold of 600 to 980 mV. |
| 5 | D | passive | Drain of the built-in power MOSFET, with a BVdss of 650 V, an absolute range of -0.3 to 650 V, and an Rdson of 0.95 Ω at Id = 2 A for the GP8521J. |
| 6 | D | passive | Drain of the built-in power MOSFET, with a BVdss of 650 V, an absolute range of -0.3 to 650 V, and an Rdson of 0.95 Ω at Id = 2 A for the GP8521J. |
| 7 | D | passive | Drain of the built-in power MOSFET, with a BVdss of 650 V, an absolute range of -0.3 to 650 V, and an Rdson of 0.95 Ω at Id = 2 A for the GP8521J. |
| 8 | D | passive | Drain of the built-in power MOSFET, with a BVdss of 650 V, an absolute range of -0.3 to 650 V, and an Rdson of 0.95 Ω at Id = 2 A for the GP8521J. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD 电源电压 supply voltage | VDD | 35 | V | 3 | |||
| CS 电流采样端 voltage | CS | -0.3 | 7 | V | 3 | ||
| FB 反馈电压输入端 voltage | FB | -0.3 | 7 | V | 3 | ||
| D 内置MOS漏端 drain voltage | D | -0.3 | 650 | V | 3 | ||
| 工作结温范围 operating junction temperature | TJ | -40 | 150 | ℃ | 3 | ||
| 工作环境温度范围 operating ambient temperature | Ta | -40 | 85 | ℃ | 3 | ||
| 储存温度范围 storage temperature | TSZG | -55 | 150 | ℃ | 3 | ||
| 最大焊接温度 maximum soldering temperature | Tlead | 260 | ℃ | soldering 10s | 3 | ||
| ESD rating | ESD | 2.5 | KV | human body model, 100pF through 1.5KΩ | 3 | ||
| 开关频率 switching frequency range (listed in 极限参数 table) | 60 | 70 | Khz | 3 | |||
| PN结到环境热阻 junction-to-ambient thermal resistance | θJA | 120 | ℃/W | 3 | |||
| PN结到管壳热阻 junction-to-case thermal resistance | θJC | 60 | ℃/W | 3 | |||
| VDD 启动电压 start-up voltage | VDD_SZ | 14.5 | 15.5 | 16.5 | V | VDD 上升 (VDD rising) | 4 |
| VDD 欠压保护阈值 UVLO threshold | VDD_UVLO | 6.5 | 7.5 | 8.5 | V | VDD 下降 (VDD falling) | 4 |
| VDD 过压保护值 OVP threshold | VDD_OVP | 37 | 38.5 | 40 | V | VDD 上升 (VDD rising) | 4 |
| VDD 启动电流 start-up current | ISZ | 5 | 10 | uA | VDD= 12.5V | 4 | |
| VDD 工作电流 operating current | IDD | 2.5 | 3.5 | mA | VFB=3V，CL=1nF | 4 | |
| 内部限流阈值 current-limit threshold (min column) | Vth_OC_min | 600 | 650 | 700 | mV | 零占空比 (zero duty cycle) | 4 |
| 内部限流阈值 current-limit threshold (max) | Vth_OC_max | 980 | mV | 4 | |||
| FB 开路电压 open-loop FB voltage | VFB_Open | 5.15 | 5.3 | 5.45 | V | 4 | |
| 标称震荡频率 nominal oscillator frequency | Fosc | 60 | 65 | 70 | Khz | 4 | |
| 频率抖动范围 frequency shuffling range | ∆F(shuffle)/Fosc | -4 | 4 | % | 4 | ||
| 频率电压偏移 frequency voltage deviation | ∆f_VDD | 5 | % | VDD = 12-25V | 4 | ||
| 频率温度偏移 frequency temperature deviation | ∆f_Temp | 5 | % | -20℃-100℃ | 5 | ||
| 最大占空比 maximum duty cycle | Duty_max | 70 | % | 5 | |||
| 软启动时间 soft-start time | Tsotfstart | 4 | ms | 4 | |||
| 前沿消隐时间 leading-edge blanking time | TLEB | 460 | ns | 4 | |||
| 过流跟踪控制延时 OC tracking delay | TD_OC | 65 | ns | CL=1nF at GATE | 4 | ||
| FB 短路电流 FB short-circuit current | IFB_Short | 0.35 | mA | 4 | |||
| PWM 输入增益 PWM input gain | AVCS | 1.6 | V/V | ΔVFB /ΔVcs | 4 | ||
| FB 驱动截止电压 skip cut-off voltage | Vskip | 1 | V | 4 | |||
| FB 功率限制阈值 power-limit threshold | VFB_OLP | 3.6 | V | 4 | |||
| OLP 触发延时 OLP debounce delay | TOLP_debounce | 56 | ms | 4 | |||
| 输入阻抗 FB input impedance | ZFB_IN | 14 | Kohm | 4 | |||
| 间歇模式基础频率 burst-mode base frequency | F_BM | 22 | Khz | 5 | |||
| OTP 进入温度 OTP enter temperature | OTP enter | 160 | ℃ | 5 | |||
| OTP 退出温度 OTP exit temperature | OTP exit | 135 | ℃ | 5 | |||
| 功率 MOS 漏源电压 drain-source breakdown voltage | BVdss | 650 | V | 5 | |||
| 静态漏源导通阻抗 static drain-source on-resistance (GP8521J) | Rdson | 0.95 | Ω | Id=2A GP8521J | 5 | ||
| 零驱动电压漏端电流 zero-gate-voltage drain current | Idss | 1 | uA | 5 |
CAD (KiCad official)
- Symbol:
GP8521J - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
gp8521j-etched.step/gp8521j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gp8521j.step/gp8521j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HaloChip datasheet (9 pp, sha256
57954280d3acc3ae, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).