component
GP8521H
Public Made by Adomby adom
HaloChip AC-DC Controllers And Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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GP8521H
HaloChip · AC-DC Controllers And Regulators · SOP-8
GP8521H from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground (芯片的地), the reference return for the controller. |
| 2 | VDD | power_in | Chip supply pin with absolute maximum rating 35 V; startup is 14.5-16.5 V (rising), UVLO threshold 6.5-8.5 V (falling), and VDD OVP 37-40 V (rising). |
| 3 | FB | input | Output voltage feedback input; absolute range -0.3 to 7 V, with open-circuit FB voltage 5.15-5.45 V and OLP power-limit threshold 3.6 V. |
| 4 | CS | input | Current sense pin; the sense resistor is connected between CS and GND, with absolute range -0.3 to 7 V and internal current limit threshold 600-700 mV at zero duty. |
| 5 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 6 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 7 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 8 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage (absolute maximum) | VDD | 35 | V | 3 | |||
| CS current-sense pin voltage | CS | -0.3 | 7 | V | 3 | ||
| FB feedback pin voltage | FB | -0.3 | 7 | V | 3 | ||
| D built-in MOS drain voltage | D | -0.3 | 650 | V | 3 | ||
| Operating junction temperature range | TJ | -40 | 150 | ℃ | 3 | ||
| Operating ambient temperature range | Ta | -40 | 85 | ℃ | 3 | ||
| Storage temperature range | TSZG | -55 | 150 | ℃ | 3 | ||
| Maximum soldering temperature | Tlead | 260 | ℃ | soldering 10s | 3 | ||
| ESD rating | ESD | 2.5 | KV | Human body model, 100pF discharged through 1.5KΩ | 3 | ||
| Switching frequency range (absolute-maximum table) | 60 | 70 | Khz | 3 | |||
| Nominal oscillator frequency | Fosc | 60 | 65 | 70 | Khz | 4 | |
| Frequency shuffling range | ∆F(shuffle)/Fosc | -4 | 4 | % | 4 | ||
| VDD start-up voltage | VDD_SZ | 14.5 | 15.5 | 16.5 | V | VDD rising | 4 |
| VDD under-voltage lockout threshold | VDD_UVLO | 6.5 | 7.5 | 8.5 | V | VDD falling | 4 |
| VDD over-voltage protection threshold | VDD_OVP | 37 | 38.5 | 40 | V | VDD rising | 4 |
| VDD start-up current | ISZ | 5 | 10 | uA | VDD = 12.5V | 4 | |
| VDD operating current | IDD | 2.5 | 3.5 | mA | VFB=3V, CL=1nF | 4 | |
| Internal current-limit threshold (minimum) | Vth_OC_min | 600 | 650 | 700 | mV | zero duty cycle | 4 |
| Internal current-limit threshold (maximum) | Vth_OC_max | 980 | mV | 4 | |||
| FB open-loop voltage | VFB_Open | 5.15 | 5.3 | 5.45 | V | 4 | |
| Maximum duty cycle | Duty_max | 70 | % | 5 | |||
| Thermal resistance, junction to ambient | θJA | 120 | ℃/W | 3 | |||
| Thermal resistance, junction to case | θJC | 60 | ℃/W | 3 |
CAD (KiCad official)
- Symbol:
GP8521H - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
gp8521h-etched.step/gp8521h-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gp8521h.step/gp8521h.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HaloChip datasheet (9 pp, sha256
0fe94550a257f4c8, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GP8521H
**HaloChip** · AC-DC Controllers And Regulators · SOP-8
GP8521H from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground (芯片的地), the reference return for the controller. |
| 2 | VDD | power_in | Chip supply pin with absolute maximum rating 35 V; startup is 14.5-16.5 V (rising), UVLO threshold 6.5-8.5 V (falling), and VDD OVP 37-40 V (rising). |
| 3 | FB | input | Output voltage feedback input; absolute range -0.3 to 7 V, with open-circuit FB voltage 5.15-5.45 V and OLP power-limit threshold 3.6 V. |
| 4 | CS | input | Current sense pin; the sense resistor is connected between CS and GND, with absolute range -0.3 to 7 V and internal current limit threshold 600-700 mV at zero duty. |
| 5 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 6 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 7 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
| 8 | D | passive | Drain of the built-in power MOSFET (内置MOS漏端), rated for a drain-source breakdown voltage (BVdss) of 650 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage (absolute maximum) | VDD | | | 35 | V | | 3 |
| CS current-sense pin voltage | CS | -0.3 | | 7 | V | | 3 |
| FB feedback pin voltage | FB | -0.3 | | 7 | V | | 3 |
| D built-in MOS drain voltage | D | -0.3 | | 650 | V | | 3 |
| Operating junction temperature range | TJ | -40 | | 150 | ℃ | | 3 |
| Operating ambient temperature range | Ta | -40 | | 85 | ℃ | | 3 |
| Storage temperature range | TSZG | -55 | | 150 | ℃ | | 3 |
| Maximum soldering temperature | Tlead | | | 260 | ℃ | soldering 10s | 3 |
| ESD rating | ESD | | | 2.5 | KV | Human body model, 100pF discharged through 1.5KΩ | 3 |
| Switching frequency range (absolute-maximum table) | | 60 | | 70 | Khz | | 3 |
| Nominal oscillator frequency | Fosc | 60 | 65 | 70 | Khz | | 4 |
| Frequency shuffling range | ∆F(shuffle)/Fosc | -4 | | 4 | % | | 4 |
| VDD start-up voltage | VDD_SZ | 14.5 | 15.5 | 16.5 | V | VDD rising | 4 |
| VDD under-voltage lockout threshold | VDD_UVLO | 6.5 | 7.5 | 8.5 | V | VDD falling | 4 |
| VDD over-voltage protection threshold | VDD_OVP | 37 | 38.5 | 40 | V | VDD rising | 4 |
| VDD start-up current | ISZ | | 5 | 10 | uA | VDD = 12.5V | 4 |
| VDD operating current | IDD | | 2.5 | 3.5 | mA | VFB=3V, CL=1nF | 4 |
| Internal current-limit threshold (minimum) | Vth_OC_min | 600 | 650 | 700 | mV | zero duty cycle | 4 |
| Internal current-limit threshold (maximum) | Vth_OC_max | | | 980 | mV | | 4 |
| FB open-loop voltage | VFB_Open | 5.15 | 5.3 | 5.45 | V | | 4 |
| Maximum duty cycle | Duty_max | | | 70 | % | | 5 |
| Thermal resistance, junction to ambient | θJA | | 120 | | ℃/W | | 3 |
| Thermal resistance, junction to case | θJC | | 60 | | ℃/W | | 3 |
## CAD (KiCad official)
- Symbol: `GP8521H`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `gp8521h-etched.step` / `gp8521h-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gp8521h.step` / `gp8521h.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HaloChip datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603377850682920960) (9 pp, sha256 `0fe94550a257f4c8`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gp8521h-datasheet.pdf)