component
GP85210
Public Made by Adomby adom
HaloChip AC-DC Controllers And Regulators, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownGP85210
HaloChip · AC-DC Controllers And Regulators · SOT-23-6
GP85210 from HaloChip, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground pin for the GP85210 controller, per the pin description table on page 2. |
| 2 | FB | input | Output voltage feedback pin with an open-circuit voltage of 5.15 V to 5.45 V, a power-limit (OLP) threshold of 3.6 V, and a 56 ms OLP debounce delay. |
| 3 | RT | input | OTP threshold adjustment pin, where an NTC resistor to GND sets over-temperature protection; 10 µA flows out of RT, OTP triggers when RT is below 1 V, and protection exits above 1.15 V. |
| 4 | CS | input | Peak current sense pin used for cycle-by-cycle current limiting, with a internal current-limit threshold of 600 mV to 700 mV at zero duty cycle and 460 ns leading-edge blanking time. |
| 5 | VDD | power_in | Chip supply pin with a start-up voltage of 14.5 V to 16.5 V, undervoltage lockout threshold of 6.5 V to 8.5 V, overvoltage protection of 37 V to 40 V, and an absolute maximum rating of 35 V. |
| 6 | GATE | output | Gate drive output for the internal MOSFET, with a high-level output of 7.5 V minimum/typical at Io=38 mA, a clamp of 16.8 V at VDD=18 V, and an absolute maximum of 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | 35 | V | 3 | |||
| CS, FB, RT voltage input | CS，FB，RT | -0.3 | 7 | V | 3 | ||
| GATE voltage (internal MOS gate) | GATE | 20 | V | 3 | |||
| Operating junction temperature range | TJ | -40 | 150 | ℃ | 3 | ||
| Operating ambient temperature range | Ta | -40 | 85 | ℃ | 3 | ||
| Storage temperature range | TSZG | -55 | 150 | ℃ | 3 | ||
| Maximum soldering temperature | Tlead | 260 | ℃ | soldering 10s | 3 | ||
| ESD (human body model) | ESD | 2.5 | KV | human body model, 100pF discharged through 1.5KΩ | 3 | ||
| Chip surface temperature limit | 135 | ℃ | 3 | ||||
| Thermal resistance, junction to ambient | θJA | 250 | ℃/W | 3 | |||
| Switching frequency | 60 | 70 | Khz | 3 | |||
| VDD start-up voltage | VDD_SZ | 14.5 | 15.5 | 16.5 | V | VDD rising | 4 |
| VDD under-voltage lockout threshold | VDD_UVLO | 6.5 | 7.5 | 8.5 | V | VDD falling | 4 |
| VDD over-voltage protection | VDD_OVP | 37 | 38.5 | 40 | V | VDD rising | 4 |
| VDD start-up current | ISZ | 5 | 10 | uA | VDD= 12.5V | 4 | |
| VDD operating current | IDD | 2.5 | 3.5 | mA | VFB=3V，CL=1nF | 4 | |
| Internal current-limit threshold at zero duty cycle | Vth_OC_min | 600 | 650 | 700 | mV | 零占空比 | 4 |
| Internal current-limit threshold (max) | Vth_OC_max | 980 | mV | 4 | |||
| FB open-loop voltage | VFB_Open | 5.15 | 5.3 | 5.45 | V | 4 | |
| Frequency shuffling range | ∆F(shuffle)/Fosc | -4 | 4 | % | 4 | ||
| Maximum duty cycle | Duty_max | 70 | % | 4 | |||
| Nominal oscillation frequency | Fosc | 60 | 65 | 70 | Khz | 4 | |
| Soft-start time | Tsotfstart | 4 | ms | 4 | |||
| Leading-edge blanking time | TLEB | 460 | ns | 4 | |||
| Over-current tracking control delay | TD_OC | 65 | ns | CL=1nF at GATE | 4 | ||
| FB short-circuit current | IFB_Short | 0.35 | mA | 4 | |||
| PWM input gain | AVCS | 1.6 | V/V | ΔVFB /ΔVcs | 4 | ||
| FB skip (burst-mode cut-off) voltage | Vskip | 1 | V | 4 | |||
| FB power-limit (OLP) threshold | VFB_OLP | 3.6 | V | 4 | |||
| OLP trigger delay | TOLP_debounce | 56 | ms | 4 | |||
| FB input impedance | ZFB_IN | 14 | Kohm | 4 | |||
| Frequency temperature deviation | ∆f_Temp | 5 | % | -20℃-100℃ | 4 | ||
| Burst-mode base frequency | F_BM | 22 | Khz | 5 | |||
| RT pin sink current | IRT_out | 10 | uA | 5 | |||
| OTP trigger voltage threshold | Vth_RT_OTP | 1 | V | 5 | |||
| Output low level | VOL | 1 | V | Io=-87mA | 5 | ||
| Output high level | VOH | 7.5 | V | Io=38mA | 5 | ||
| Output clamp level | VG_clamp | 16.8 | V | VDD=18V | 5 | ||
| Gate output rise time | T_r | 730 | ns | CL=1nF, Gate从1V上升到15V | 5 | ||
| Gate output fall time | T_f | 59 | ns | CL=1nF, Gate从15V到1V | 5 |
CAD (KiCad official)
- Symbol:
GP85210 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
gp85210-etched.step/gp85210-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gp85210.step/gp85210.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HaloChip datasheet (9 pp, sha256
26010edab728cc8f, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).