component

GP7596B

Public Made by Adom

by adom

HaloChip Synchronous Rectifier Controllers, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)gp7596b
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs gp7596b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
viewers gp7596b: viewers · Ray 26d ago
gp7596b-etched.fit.json gp7596b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
gp7596b-etched.glb gp7596b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
gp7596b-etched.step gp7596b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
gp7596b.glb Publish 0.1.0 · Ray 26d ago
gp7596b.kicad_mod Publish 0.1.0 · Ray 26d ago
gp7596b.kicad_sym Publish 0.1.0 · Ray 26d ago
gp7596b.lbr Publish 0.1.0 · Ray 26d ago
gp7596b.step Publish 0.1.0 · Ray 26d ago
package.json Publish 0.1.0 · Ray 26d ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md gp7596b: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago

GP7596B

HaloChip · Synchronous Rectifier Controllers · SOP-8

GP7596B from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Chip ground. Tied together internally with pins 2 and 3. Used as the return for the internal control logic in the 'floating-ground' SR architecture.
2 GND power_in Chip ground. Tied together internally with pins 1 and 3.
3 GND power_in Chip ground. Tied together internally with pins 1 and 2.
4 VCC power_in Chip supply, nominally 5 V (abs-max 6 V, clamp ~6 V @ 20 mA). Bypass locally with ~1 µF. Fed by the internal HV LDO from SW, so no auxiliary winding is needed. UVLO(ON)=3.7 V, UVLO(OFF)=2.8 V.
5 SW power_out Drain of the internal synchronous-rectifier power MOSFET. Tied together internally with pins 6, 7 and 8 to carry the SR current. Absolute-max 65 V, recommended 4.7-60 V, 15 A continuous / 30 A pulsed.
6 SW power_out Drain of the internal SR power MOSFET (tied to pins 5, 7, 8).
7 SW power_out Drain of the internal SR power MOSFET (tied to pins 5, 6, 8).
8 SW power_out Drain of the internal SR power MOSFET (tied to pins 5, 6, 7). Also feeds the internal HV LDO that generates VCC.

Key specifications

Parameter Value
Manufacturer HaloChip
Package SOP-8
Category Power Management (PMIC)
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • GP7596B
  • GP7596BA
  • GP7596BB
  • GP7596A
  • GP7596AA
  • GP7596AB
  • GP7596C
  • GP7596CA
  • GP7596CB

CAD (KiCad official)

  • Symbol: GP7596B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: gp7596b-etched.step / gp7596b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gp7596b.step / gp7596b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HaloChip datasheet (7 pp, sha256 c7e9e6914030b64f, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF