component
GP7596A
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HaloChip Synchronous Rectifier Controllers, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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GP7596A
HaloChip · Synchronous Rectifier Controllers · SOP-8
GP7596A from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground. Return for the internal control logic and driver, and source of the internal power MOSFET (floating-ground / GP7596X pinout variant). |
| 2 | GND | power_in | Chip ground. Tied internally to pins 1 and 3; parallel these pins to the ground plane to reduce inductance to the MOSFET source. |
| 3 | GND | power_in | Chip ground. Tied internally to pins 1 and 2. |
| 4 | VCC | power_in | Chip supply pin, nominally 5 V (UVLO on 3.7 V, UVLO off 2.8 V, internally clamped to 6 V at 20 mA). Place a bypass capacitor (typ. 1 µF) close to this pin; the internal HV LDO charges VCC from SW/SWS so no auxiliary winding is needed. |
| 5 | SW | power_out | Drain of the integrated synchronous-rectifier power MOSFET. Operating drain-source voltage rated to 65 V (recommended 4.7-60 V); RDS(on) 18 mΩ for the GP7596A. Tie pins 5-8 in parallel to carry the SR current with minimum resistance. |
| 6 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 7, 8. |
| 7 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 6, 8. |
| 8 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 6, 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
GP7596AGP7596AAGP7596ABGP7596BGP7596BAGP7596BBGP7596CGP7596CAGP7596CB
CAD (KiCad official)
- Symbol:
GP7596A - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
gp7596a-etched.step/gp7596a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gp7596a.step/gp7596a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HaloChip datasheet (7 pp, sha256
c7e9e6914030b64f, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GP7596A
**HaloChip** · Synchronous Rectifier Controllers · SOP-8
GP7596A from HaloChip, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Chip ground. Return for the internal control logic and driver, and source of the internal power MOSFET (floating-ground / GP7596X pinout variant). |
| 2 | GND | power_in | Chip ground. Tied internally to pins 1 and 3; parallel these pins to the ground plane to reduce inductance to the MOSFET source. |
| 3 | GND | power_in | Chip ground. Tied internally to pins 1 and 2. |
| 4 | VCC | power_in | Chip supply pin, nominally 5 V (UVLO on 3.7 V, UVLO off 2.8 V, internally clamped to 6 V at 20 mA). Place a bypass capacitor (typ. 1 µF) close to this pin; the internal HV LDO charges VCC from SW/SWS so no auxiliary winding is needed. |
| 5 | SW | power_out | Drain of the integrated synchronous-rectifier power MOSFET. Operating drain-source voltage rated to 65 V (recommended 4.7-60 V); RDS(on) 18 mΩ for the GP7596A. Tie pins 5-8 in parallel to carry the SR current with minimum resistance. |
| 6 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 7, 8. |
| 7 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 6, 8. |
| 8 | SW | power_out | Drain of the integrated power MOSFET. Tied internally to pins 5, 6, 7. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HaloChip |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `GP7596A`
- `GP7596AA`
- `GP7596AB`
- `GP7596B`
- `GP7596BA`
- `GP7596BB`
- `GP7596C`
- `GP7596CA`
- `GP7596CB`
## CAD (KiCad official)
- Symbol: `GP7596A`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `gp7596a-etched.step` / `gp7596a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gp7596a.step` / `gp7596a.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HaloChip datasheet](docs/gp7596a-datasheet.pdf) (7 pp, sha256 `c7e9e6914030b64f`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gp7596a-datasheet.pdf)