component
GN574D
Public Made by Adomby adom
GN Semic Shift Registers, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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GN574D
GN Semic · Shift Registers · SOP-20-300mil
GN574D from GN Semic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Three-state output enable input, active low; when OE is high the Q0 to Q7 outputs are forced to high impedance (Z). |
| 2 | D0 | input | Data input 0 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 3 | D1 | input | Data input 1 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 4 | D2 | input | Data input 2 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 5 | D3 | input | Data input 3 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 6 | D4 | input | Data input 4 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 7 | D5 | input | Data input 5 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 8 | D6 | input | Data input 6 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 9 | D7 | input | Data input 7 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 10 | GND | power_in | System ground (0 V) reference for the device. |
| 11 | CP | input | Clock input, low-to-high edge triggered; loads the D inputs into the flip-flops on the rising edge. |
| 12 | Q7 | tri_state | Non-inverting three-state data output 7, high impedance when OE is high. |
| 13 | Q6 | tri_state | Non-inverting three-state data output 6, high impedance when OE is high. |
| 14 | Q5 | tri_state | Non-inverting three-state data output 5, high impedance when OE is high. |
| 15 | Q4 | tri_state | Non-inverting three-state data output 4, high impedance when OE is high. |
| 16 | Q3 | tri_state | Non-inverting three-state data output 3, high impedance when OE is high. |
| 17 | Q2 | tri_state | Non-inverting three-state data output 2, high impedance when OE is high. |
| 18 | Q1 | tri_state | Non-inverting three-state data output 1, high impedance when OE is high. |
| 19 | Q0 | tri_state | Non-inverting three-state data output 0, high impedance when OE is high. |
| 20 | VCC | power_in | Positive power supply; recommended supply range is 2.0 V to 6.0 V (typical 5.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GN Semic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (VCC supply voltage) | VCC | -0.5 | 7 | V | 3 | ||
| 输入钳位电流 (Input clamp current) | Ilk | -20 | 20 | mA | V1 <-0.5V or V1 >Vcc+0.5V | 3 | |
| 输出钳位电流 (Output clamp current) | Iok | -20 | 20 | mA | Vo<-0.5V or Vo>Vcc+0.5V | 3 | |
| 输出端或接收端电流 (Output current) | Io | -35 | 35 | mA | -0.5V<Vo<Vcc+0.5V | 3 | |
| VCC 或 GND 电流 (VCC or GND current) | Icc, IGND | -70 | 70 | mA | 3 | ||
| 贮存温度 (Storage temperature) | Tstg | -65 | 150 | ℃ | 3 | ||
| 功率损耗 (Power dissipation, SOP package) | PD | 500 | mW | Tamb=-40 to +125℃; SOP package (note 2) | 3 | ||
| 焊接温度 (Soldering temperature, SOP) | TL | 250 | ℃ | 10 s, SOP | 3 | ||
| 电源电压 (VCC supply voltage) | VCC | 2 | 5 | 6 | V | 3 | |
| 输入电压 (Input voltage) | Vi | 0 | V | 3 | |||
| 输出电压 (Output voltage) | Vo | 0 | V | 3 | |||
| 工作环境温度 (Operating ambient temperature) | Tamb | -40 | 25 | 85 | ℃ | 3 | |
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | 1000 | ns | Vcc=2.0V | 3 | ||
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | 6 | 500 | ns | Vcc=4.5V | 3 | |
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | 400 | ns | Vcc=6.0V | 3 | ||
| 输入高电平电压 (Input high-level voltage) | VIH | 1.5 | V | VCC=2.0V; Tamb=-40 to +85 °C | 4 | ||
| 输入高电平电压 (Input high-level voltage) | VIH | 3.15 | V | VCC=4.5V; Tamb=-40 to +85 °C | 4 | ||
| 输入高电平电压 (Input high-level voltage) | VIH | 4.2 | V | VCC=6.0V; Tamb=-40 to +85 °C | 4 | ||
| 输入低电平电压 (Input low-level voltage) | VIL | 0.5 | V | VCC=2.0V; Tamb=-40 to +85 °C | 4 | ||
| 输入低电平电压 (Input low-level voltage) | VIL | 1.35 | V | VCC=4.5V; Tamb=-40 to +85 °C | 4 | ||
| 输入低电平电压 (Input low-level voltage) | VIL | 1.8 | V | VCC=6.0V; Tamb=-40 to +85 °C | 4 | ||
| 输出高电平电压 (Output high-level voltage) | VOH | 1.9 | V | Vi=VIH或VIL, VCC=2.0V, IO=-20uA; Tamb=-40 to +85 °C | 4 | ||
| 输出高电平电压 (Output high-level voltage) | VOH | 4.4 | V | Vi=VIH或VIL, VCC=4.5V, IO=-20uA; Tamb=-40 to +85 °C | 4 | ||
| 输出高电平电压 (Output high-level voltage) | VOH | 3.84 | V | Vi=VIH或VIL, VCC=4.5V, IO=-6.0mA; Tamb=-40 to +85 °C | 4 | ||
| 输出高电平电压 (Output high-level voltage) | VOH | 5.9 | V | Vi=VIH或VIL, VCC=6.0V, IO=-20uA; Tamb=-40 to +85 °C | 4 | ||
| 输出高电平电压 (Output high-level voltage) | VOH | 5.34 | V | Vi=VIH或VIL, VCC=6.0V, IO=-7.8mA; Tamb=-40 to +85 °C | 4 | ||
| 输出低电平电压 (Output low-level voltage) | VOL | 0.1 | V | Vi=VIH或VIL, VCC=2.0V, IO=20uA; Tamb=-40 to +85 °C | 4 | ||
| 输出低电平电压 (Output low-level voltage) | VOL | 0.33 | V | Vi=VIH或VIL, VCC=4.5V, IO=6.0mA; Tamb=-40 to +85 °C | 4 | ||
| 输入漏电流 (Input leakage current) | ILI | -1 | 1 | uA | Vi=VCC 或 GND, VCC=6.0V; Tamb=-40 to +85 °C | 4 | |
| 截止状态输出电流 (Off-state output current) | IOZ | -5 | 5 | uA | Vi=VIH或VIL, Vo=VCC或GND, VCC=6.0V; Tamb=-40 to +85 °C | 4 | |
| 静态电流 (Quiescent supply current) | ICC | 80 | uA | Vi=VCC 或 GND, VCC=6.0V, IO=0; Tamb=-40 to +85 °C | 4 | ||
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | 190 | ns | 见图 3; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | 35 | ns | 见图 3; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | 33 | ns | 见图 3; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | 175 | ns | 见图 4; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | 35 | ns | 见图 4; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | 30 | ns | 见图 4; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | 155 | ns | 见图 4; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | 31 | ns | 见图 4; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | 26 | ns | 见图 4; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 输出转换时间 (Output transition time) | tTHL/tTLH | 75 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 输出转换时间 (Output transition time) | tTHL/tTLH | 15 | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 输出转换时间 (Output transition time) | tTHL/tTLH | 13 | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 100 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 20 | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 17 | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 75 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 15 | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 13 | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| Dn 到 CP 保持时间 (Dn to CP hold time) | th | 5 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 4.8 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 24 | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 | ||
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 28 | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
CAD (KiCad official)
- Symbol:
GN574D - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gn574d-etched.step/gn574d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gn574d.step/gn574d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GN Semic datasheet (12 pp, sha256
0b498dfafe0c11c9, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GN574D
**GN Semic** · Shift Registers · SOP-20-300mil
GN574D from GN Semic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Three-state output enable input, active low; when OE is high the Q0 to Q7 outputs are forced to high impedance (Z). |
| 2 | D0 | input | Data input 0 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 3 | D1 | input | Data input 1 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 4 | D2 | input | Data input 2 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 5 | D3 | input | Data input 3 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 6 | D4 | input | Data input 4 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 7 | D5 | input | Data input 5 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 8 | D6 | input | Data input 6 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 9 | D7 | input | Data input 7 for the octal D flip-flop, sampled on the rising edge of CP; recommended input voltage range is 0 V to VCC. |
| 10 | GND | power_in | System ground (0 V) reference for the device. |
| 11 | CP | input | Clock input, low-to-high edge triggered; loads the D inputs into the flip-flops on the rising edge. |
| 12 | Q7 | tri_state | Non-inverting three-state data output 7, high impedance when OE is high. |
| 13 | Q6 | tri_state | Non-inverting three-state data output 6, high impedance when OE is high. |
| 14 | Q5 | tri_state | Non-inverting three-state data output 5, high impedance when OE is high. |
| 15 | Q4 | tri_state | Non-inverting three-state data output 4, high impedance when OE is high. |
| 16 | Q3 | tri_state | Non-inverting three-state data output 3, high impedance when OE is high. |
| 17 | Q2 | tri_state | Non-inverting three-state data output 2, high impedance when OE is high. |
| 18 | Q1 | tri_state | Non-inverting three-state data output 1, high impedance when OE is high. |
| 19 | Q0 | tri_state | Non-inverting three-state data output 0, high impedance when OE is high. |
| 20 | VCC | power_in | Positive power supply; recommended supply range is 2.0 V to 6.0 V (typical 5.0 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GN Semic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (VCC supply voltage) | VCC | -0.5 | | 7 | V | | 3 |
| 输入钳位电流 (Input clamp current) | Ilk | -20 | | 20 | mA | V1 <-0.5V or V1 >Vcc+0.5V | 3 |
| 输出钳位电流 (Output clamp current) | Iok | -20 | | 20 | mA | Vo<-0.5V or Vo>Vcc+0.5V | 3 |
| 输出端或接收端电流 (Output current) | Io | -35 | | 35 | mA | -0.5V<Vo<Vcc+0.5V | 3 |
| VCC 或 GND 电流 (VCC or GND current) | Icc, IGND | -70 | | 70 | mA | | 3 |
| 贮存温度 (Storage temperature) | Tstg | -65 | | 150 | ℃ | | 3 |
| 功率损耗 (Power dissipation, SOP package) | PD | | | 500 | mW | Tamb=-40 to +125℃; SOP package (note 2) | 3 |
| 焊接温度 (Soldering temperature, SOP) | TL | | | 250 | ℃ | 10 s, SOP | 3 |
| 电源电压 (VCC supply voltage) | VCC | 2 | 5 | 6 | V | | 3 |
| 输入电压 (Input voltage) | Vi | 0 | | | V | | 3 |
| 输出电压 (Output voltage) | Vo | 0 | | | V | | 3 |
| 工作环境温度 (Operating ambient temperature) | Tamb | -40 | 25 | 85 | ℃ | | 3 |
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | | | 1000 | ns | Vcc=2.0V | 3 |
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | | 6 | 500 | ns | Vcc=4.5V | 3 |
| 输入上升和下降时间 (Input rise and fall time) | tr, tf | | | 400 | ns | Vcc=6.0V | 3 |
| 输入高电平电压 (Input high-level voltage) | VIH | 1.5 | | | V | VCC=2.0V; Tamb=-40 to +85 °C | 4 |
| 输入高电平电压 (Input high-level voltage) | VIH | 3.15 | | | V | VCC=4.5V; Tamb=-40 to +85 °C | 4 |
| 输入高电平电压 (Input high-level voltage) | VIH | 4.2 | | | V | VCC=6.0V; Tamb=-40 to +85 °C | 4 |
| 输入低电平电压 (Input low-level voltage) | VIL | | | 0.5 | V | VCC=2.0V; Tamb=-40 to +85 °C | 4 |
| 输入低电平电压 (Input low-level voltage) | VIL | | | 1.35 | V | VCC=4.5V; Tamb=-40 to +85 °C | 4 |
| 输入低电平电压 (Input low-level voltage) | VIL | | | 1.8 | V | VCC=6.0V; Tamb=-40 to +85 °C | 4 |
| 输出高电平电压 (Output high-level voltage) | VOH | 1.9 | | | V | Vi=VIH或VIL, VCC=2.0V, IO=-20uA; Tamb=-40 to +85 °C | 4 |
| 输出高电平电压 (Output high-level voltage) | VOH | 4.4 | | | V | Vi=VIH或VIL, VCC=4.5V, IO=-20uA; Tamb=-40 to +85 °C | 4 |
| 输出高电平电压 (Output high-level voltage) | VOH | 3.84 | | | V | Vi=VIH或VIL, VCC=4.5V, IO=-6.0mA; Tamb=-40 to +85 °C | 4 |
| 输出高电平电压 (Output high-level voltage) | VOH | 5.9 | | | V | Vi=VIH或VIL, VCC=6.0V, IO=-20uA; Tamb=-40 to +85 °C | 4 |
| 输出高电平电压 (Output high-level voltage) | VOH | 5.34 | | | V | Vi=VIH或VIL, VCC=6.0V, IO=-7.8mA; Tamb=-40 to +85 °C | 4 |
| 输出低电平电压 (Output low-level voltage) | VOL | | | 0.1 | V | Vi=VIH或VIL, VCC=2.0V, IO=20uA; Tamb=-40 to +85 °C | 4 |
| 输出低电平电压 (Output low-level voltage) | VOL | | | 0.33 | V | Vi=VIH或VIL, VCC=4.5V, IO=6.0mA; Tamb=-40 to +85 °C | 4 |
| 输入漏电流 (Input leakage current) | ILI | -1 | | 1 | uA | Vi=VCC 或 GND, VCC=6.0V; Tamb=-40 to +85 °C | 4 |
| 截止状态输出电流 (Off-state output current) | IOZ | -5 | | 5 | uA | Vi=VIH或VIL, Vo=VCC或GND, VCC=6.0V; Tamb=-40 to +85 °C | 4 |
| 静态电流 (Quiescent supply current) | ICC | | | 80 | uA | Vi=VCC 或 GND, VCC=6.0V, IO=0; Tamb=-40 to +85 °C | 4 |
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | | | 190 | ns | 见图 3; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | | | 35 | ns | 见图 3; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| CP 到 Qn 的传输延时 (CP to Qn propagation delay) | tPHL/tPLH | | | 33 | ns | 见图 3; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | | | 175 | ns | 见图 4; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | | | 35 | ns | 见图 4; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出始能时间 (OE to Qn enable time) | tPZH/tPZl | | | 30 | ns | 见图 4; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | | | 155 | ns | 见图 4; VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | | | 31 | ns | 见图 4; VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| OE 到 Qn 三态输出截止时间 (OE to Qn disable time) | tPZH/tPZl | | | 26 | ns | 见图 4; VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 输出转换时间 (Output transition time) | tTHL/tTLH | | | 75 | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 输出转换时间 (Output transition time) | tTHL/tTLH | | | 15 | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 输出转换时间 (Output transition time) | tTHL/tTLH | | | 13 | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 100 | | | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 20 | | | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟高或低脉冲宽度 (Clock pulse width, high or low) | tW | 17 | | | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 75 | | | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 15 | | | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| Dn 到 CP 建立时间 (Dn to CP setup time) | tSU | 13 | | | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| Dn 到 CP 保持时间 (Dn to CP hold time) | th | 5 | | | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 4.8 | | | ns | VCC=2.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 24 | | | ns | VCC=4.5V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
| 时钟脉冲最大频率 (Clock pulse maximum frequency, as printed) | fmax | 28 | | | ns | VCC=6.0V, CL=50pF, tr=tf=6.0ns; Tamb=-40 to +85℃ | 5 |
## CAD (KiCad official)
- Symbol: `GN574D`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `gn574d-etched.step` / `gn574d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gn574d.step` / `gn574d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GN Semic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884221838430208) (12 pp, sha256 `0b498dfafe0c11c9`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gn574d-datasheet.pdf)