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Initial commit: component/gn573d

Ray ·fcea34f823 ·4d ago
2 files changed +282
README.mdadded+57
@@ -0,0 +1,57 @@+# GN573D++**GN Semic** · Latches · SOP-20++GN573D from GN Semic, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Tri-state output enable input (active low); high level places all outputs in high-impedance state. |+| 2 | D0 | input | Data input for bit 0 of the 8-bit latch. |+| 3 | D1 | input | Data input for bit 1 of the 8-bit latch. |+| 4 | D2 | input | Data input for bit 2 of the 8-bit latch. |+| 5 | D3 | input | Data input for bit 3 of the 8-bit latch. |+| 6 | D4 | input | Data input for bit 4 of the 8-bit latch. |+| 7 | D5 | input | Data input for bit 5 of the 8-bit latch. |+| 8 | D6 | input | Data input for bit 6 of the 8-bit latch. |+| 9 | D7 | input | Data input for bit 7 of the 8-bit latch. |+| 10 | GND | power_in | Ground reference (0V). |+| 11 | LE | input | Latch enable input (active high); high level enables transparent mode where outputs follow inputs, low level latches data at setup time before LE falling edge. |+| 12 | Q7 | tri_state | Tri-state latch output for bit 7 driven by D7; controlled by OE signal. |+| 13 | Q6 | tri_state | Tri-state latch output for bit 6 driven by D6; controlled by OE signal. |+| 14 | Q5 | tri_state | Tri-state latch output for bit 5 driven by D5; controlled by OE signal. |+| 15 | Q4 | tri_state | Tri-state latch output for bit 4 driven by D4; controlled by OE signal. |+| 16 | Q3 | tri_state | Tri-state latch output for bit 3 driven by D3; controlled by OE signal. |+| 17 | Q2 | tri_state | Tri-state latch output for bit 2 driven by D2; controlled by OE signal. |+| 18 | Q1 | tri_state | Tri-state latch output for bit 1 driven by D1; controlled by OE signal. |+| 19 | Q0 | tri_state | Tri-state latch output for bit 0 driven by D0; controlled by OE signal. |+| 20 | VCC | power_in | Supply voltage with recommended operating range 2.0V to 6.0V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GN Semic |+| Package | SOP-20 |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `GN573D`+- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`+- 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `gn573d-etched.step` / `gn573d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gn573d.step` / `gn573d.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GN Semic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603385992989077504) (14 pp, sha256 `79ffe808e66961b6`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/gn573d-datasheet.pdf)
page.jsonadded+225
@@ -0,0 +1,225 @@+{+  "slug": "gn573d",+  "version": "0.1.0",+  "type": "component",+  "description": "GN Semic Latches, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "gn573d",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "gn573d.kicad_sym",+    "gn573d.kicad_mod",+    "gn573d.glb",+    "gn573d.step",+    "gn573d.lbr",+    "docs/hero.png",+    "docs/gn573d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "GN573D",+    "manufacturer": "GN Semic",+    "package": "SOP-20",+    "pin_count": 20,+    "category": "Logic",+    "subcategory": "Latches",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603385992989077504",+    "parts": {+      "symbol": "gn573d.kicad_sym",+      "footprint": "gn573d.kicad_mod",+      "model_3d": "gn573d-etched.glb",+      "model_3d_plain": "gn573d.glb",+      "model_3d_step": "gn573d-etched.step",+      "model_3d_step_plain": "gn573d.step",+      "lbr": "gn573d.lbr"+    },+    "distributor_links": {+      "lcsc": "C22461435"+    },+    "distributor_check": {+      "checked_at": "2026-10-01T17:33:10Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": null,+        "status": "no match"+      },+      "mouser": {+        "pn": null,+        "status": "no match"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "OE",+        "type": "input",+        "description": "Tri-state output enable input (active low); high level places all outputs in high-impedance state."+      },+      {+        "number": "2",+        "name": "D0",+        "type": "input",+        "description": "Data input for bit 0 of the 8-bit latch."+      },+      {+        "number": "3",+        "name": "D1",+        "type": "input",+        "description": "Data input for bit 1 of the 8-bit latch."+      },+      {+        "number": "4",+        "name": "D2",+        "type": "input",+        "description": "Data input for bit 2 of the 8-bit latch."+      },+      {+        "number": "5",+        "name": "D3",+        "type": "input",+        "description": "Data input for bit 3 of the 8-bit latch."+      },+      {+        "number": "6",+        "name": "D4",+        "type": "input",+        "description": "Data input for bit 4 of the 8-bit latch."+      },+      {+        "number": "7",+        "name": "D5",+        "type": "input",+        "description": "Data input for bit 5 of the 8-bit latch."+      },+      {+        "number": "8",+        "name": "D6",+        "type": "input",+        "description": "Data input for bit 6 of the 8-bit latch."+      },+      {+        "number": "9",+        "name": "D7",+        "type": "input",+        "description": "Data input for bit 7 of the 8-bit latch."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0V)."+      },+      {+        "number": "11",+        "name": "LE",+        "type": "input",+        "description": "Latch enable input (active high); high level enables transparent mode where outputs follow inputs, low level latches data at setup time before LE falling edge."+      },+      {+        "number": "12",+        "name": "Q7",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 7 driven by D7; controlled by OE signal."+      },+      {+        "number": "13",+        "name": "Q6",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 6 driven by D6; controlled by OE signal."+      },+      {+        "number": "14",+        "name": "Q5",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 5 driven by D5; controlled by OE signal."+      },+      {+        "number": "15",+        "name": "Q4",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 4 driven by D4; controlled by OE signal."+      },+      {+        "number": "16",+        "name": "Q3",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 3 driven by D3; controlled by OE signal."+      },+      {+        "number": "17",+        "name": "Q2",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 2 driven by D2; controlled by OE signal."+      },+      {+        "number": "18",+        "name": "Q1",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 1 driven by D1; controlled by OE signal."+      },+      {+        "number": "19",+        "name": "Q0",+        "type": "tri_state",+        "description": "Tri-state latch output for bit 0 driven by D0; controlled by OE signal."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage with recommended operating range 2.0V to 6.0V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 14,+        "cost_usd": 0.2544,+        "at": "2026-10-01T17:32:48"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603385992989077504",+        "pages": 14,+        "sha256": "79ffe808e66961b6",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file