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GM1203AACPZ-2-R7
Public Made by Adomby adom
GONGMOSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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GM1203AACPZ-2-R7
GONGMOSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(5x5)
GM1203AACPZ-2-R7 from GONGMOSEMI, in a QFN-20(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND should be placed as close to the pin as possible for stability. |
| 2 | NC | unconnected | Not connected. |
| 3 | NC | unconnected | Not connected. |
| 4 | NC | unconnected | Not connected. |
| 5 | IN | power_in | Input supply; operating input range is 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) to GND placed close to the pins. |
| 6 | IN | power_in | Input supply; operating input range is 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) to GND placed close to the pins. |
| 7 | IN | power_in | Input supply; operating input range is 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) to GND placed close to the pins. |
| 8 | IN | power_in | Input supply; operating input range is 1.1 V to 6.5 V, with a 10 µF or larger ceramic capacitor (5 µF minimum) to GND placed close to the pins. |
| 9 | PG | output | Open-drain, active-high power-good output that requires an external 10 kΩ to 100 kΩ pull-up; absolute maximum PG current is −5 mA. |
| 10 | BIAS | input | Bias supply that lowers headroom dissipation and improves DC/AC performance at VIN ≤ 2.2 V; a 10 µF or larger capacitor to GND is required, and the pin must be floating or grounded if unused. |
| 11 | EN | input | Enable input: above 1.1 V enables the regulator and below 0.4 V disables it; tie to IN or BIAS if enable control is not needed. |
| 12 | GND | power_in | Ground; must be connected with low impedance to the exposed thermal pad. |
| 13 | NC | unconnected | Not connected. |
| 14 | NC | unconnected | Not connected. |
| 15 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor to GND (10 nF or more recommended) lowers reference noise and sets the soft-start ramp, with absolute maximum voltage of −0.3 V to +3.6 V. |
| 16 | FB | input | Feedback pin to the error amplifier; a 10 nF feed-forward capacitor between FB and OUT is recommended, with absolute maximum voltage of −0.3 V to +3.6 V and leakage of ±100 nA. |
| 17 | NC | unconnected | Not connected. |
| 18 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND should be placed as close to the pin as possible for stability. |
| 19 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND should be placed as close to the pin as possible for stability. |
| 20 | OUT | power_out | Regulated output; a 47 µF or larger ceramic capacitor to GND should be placed as close to the pin as possible for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GONGMOSEMI |
| Package | QFN-20(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| UVLO rising threshold with BIAS | VUVLO | 0.98 | 1.085 | V | VBIAS = 3.0 V, TJ = −40°C to +125°C | 9 | |
| UVLO rising threshold without BIAS | VUVLO1 | 1.32 | 1.49 | V | TJ = −40°C to +125°C, VIN rising | 9 | |
| Minimum BIAS input voltage | VBIAS_UVLO | 2.2 | 2.9 | V | VIN = 1.1 V, VBIAS rising | 9 | |
| Output voltage range, pin-programmed (GM1203A) | VFB | 0.5 | 3.65 | V | 使用引脚编程 (pin-programmed) | 9 | |
| Output voltage range, external resistor (GM1203A) | VFB | 0.5 | 5.5 | V | 使用外部电阻 (external resistor divider) | 9 | |
| Output voltage accuracy | -1 | 1 | % | 0.5 V ≤ VOUT ≤ 3.65 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 9 | ||
| Output voltage accuracy with BIAS | -1 | 1.3 | % | VIN = 1.1 V, VOUT = 0.5V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 9 | ||
| Dropout voltage, 3 A | VDO | 140 | 260 | mV | VIN = 1.5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3 A | VDO | 115 | 220 | mV | VIN = 5.4 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3 A with BIAS | VDO | 120 | 210 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Output current limit | ILIM | 3.7 | 4.2 | 6.7 | A | VOUT forced to 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 9 |
| EN low-level input voltage | VEN_IL | 0 | 0.4 | V | 9 | ||
| EN high-level input voltage | VEN_IH | 1.1 | 6.5 | V | 9 | ||
| EN pin current | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 9 | |
| PG falling threshold | VPG_FALLING | 82 | 91 | 93 | % × VOUT | 9 | |
| NR/SS charging current | INR/SS | 4 | 9 | 11.5 | µA | VNR/SS = GND, VIN = 6.5 V | 9 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 9 | |
| IN, BIAS, PG, EN voltage to GND | -0.3 | 7 | V | 8 | |||
| SNS, OUT voltage to GND | -0.3 | V | max printed as VIN+0.3 V | 8 | |||
| NR/SS, FB voltage to GND | -0.3 | 3.6 | V | 8 | |||
| 50mV-800mV output-setting pins voltage to GND | -0.3 | V | max printed as VOUT+0.3 V | 8 | |||
| PG current | -5 | mA | 8 | ||||
| Storage temperature range | -65 | 150 | °C | 8 | |||
| Operating temperature range | -40 | 125 | °C | 8 | |||
| Maximum continuous junction temperature | TJ | 125 | °C | continuous operation | 15 | ||
| Input voltage operating range | VIN | 1.1 | 6.5 | V | 15 | ||
| Output capacitor | COUT | 47 | µF | ceramic, OUT to GND, 22 µF or more effective | 18 | ||
| Input capacitor | CIN | 10 | µF | ceramic, IN to GND | 18 | ||
| UVLO hysteresis with BIAS | VUVLO_HYS | 100 | mV | VBIAS = 3.0 V | 9 | ||
| UVLO rising threshold, alternate row | VUVLO1 | 1.59 | V | VIN rising | 9 | ||
| UVLO hysteresis without BIAS | VUVLO1_HYS | 115 | mV | 9 | |||
| BIAS UVLO hysteresis | VBIAS_UVLO_HYS | 200 | mV | VIN = 1.1 V | 9 | ||
| GND pin current, quiescent | IGND | 15 | mA | VIN = 6.5 V, IOUT = 5 mA | 9 | ||
| GND pin current, shutdown | IGND | 18 | µA | Shutdown, VIN = 6.5 V, VEN = 0.5 V | 9 | ||
| BIAS pin current | IBIAS | 16 | mA | VIN = 1.1 V, VBIAS = 6.5 V, VOUT = 0.8 V, IOUT = 3 A | 9 | ||
| Line regulation | ΔVOUT/ΔVIN | 0.1 | mV/V | VIN = Max(VOUT + 0.4V, 1.5 V) to 6.5 V | 9 | ||
| Load regulation | ΔVOUT/ΔIOUT | 0.2 | mV/A | 5 mA ≤ IOUT ≤ 3 A | 9 | ||
| PG threshold hysteresis | VPG_HYS | 2 | % × VOUT | rising | 9 | ||
| PG low-level output voltage | VPG_OL | 0.4 | V | VOUT < VPG_FALLING, IPG = -1 mA | 9 | ||
| PG leakage current | IPG_LK | 1 | µA | VOUT > VPG_FALLING + VPG_HYS, VPG = 6.5 V | 9 | ||
| NR/SS pin voltage | VNR/SS | 0.5 | V | 9 | |||
| Power supply rejection ratio | PSRR | 68 | dB | VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF, f = 10 kHz, VOUT = 0.8 V, VBIAS = 5.0 V | 9 | ||
| Power supply rejection ratio | PSRR | 51 | dB | VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF, f = 1 MHz, VOUT = 0.8 V, VBIAS = 5.0 V | 9 | ||
| Power supply rejection ratio | PSRR | 58 | dB | VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF, f = 10 kHz, VOUT = 5.0 V | 9 | ||
| Power supply rejection ratio | PSRR | 43 | dB | VIN, VOUT = 0.4 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF, f = 1 MHz, VOUT = 5.0 V | 9 | ||
| Output noise voltage | VN | 3 | µVRMS | BW = 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.5 V or 0.8 V, VBIAS = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 9 | ||
| Output noise voltage | VN | 14.8 | µVRMS | BW = 10 Hz to 100 kHz, VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF | 9 | ||
| Thermal shutdown threshold | TSD | 150 | °C | Junction temperature rising | 9 | ||
| Thermal shutdown hysteresis | TSD_HYS | 20 | °C | Junction temperature falling | 9 | ||
| Junction-to-ambient thermal resistance, 20-pin 5 mm × 5 mm QFN | θJA | 35.4 | °C/W | Worst case, board-mounted, JEDEC high-K board | 8 |
CAD (KiCad official)
- Symbol:
GM1203AACPZ-2-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: QFN-20(5x5) (KiCad packages3D, STEP)
- 3D model files:
gm1203aacpz-2-r7-etched.step/gm1203aacpz-2-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gm1203aacpz-2-r7.step/gm1203aacpz-2-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GONGMOSEMI datasheet (25 pp, sha256
f744d3090b584d94, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).