component
GM1203AACPZ-1-R7
Public Made by Adomby adom
GONGMOSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20-EP(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownGM1203AACPZ-1-R7
GONGMOSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20-EP(3.5x3.5)
GM1203AACPZ-1-R7 from GONGMOSEMI, in a QFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin; a ceramic capacitor of 47 µF or greater from this pin to GND, placed as close to the pin as possible, is required for stability. |
| 2 | SNS | passive | Output sense pin connected to the output through an internal R0 resistor; connect it to the load side of the output only when the VOUT programming function is used, otherwise leave it floating. |
| 3 | FB | input | Feedback pin to the error amplifier; a 10 nF feed-forward capacitor from FB to OUT, placed as close to the device as possible, is recommended for best AC performance. |
| 4 | PG | output | Open-drain power-good output (active high) that indicates the output has reached the PG rising threshold; an external pull-up of 10 kΩ to 100 kΩ is recommended and PG sink current is limited to -5 mA in absolute maximum ratings. |
| 5 | 50mV | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating to set the output voltage, with GND adding 50 mV to the output. |
| 6 | 100mV | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating, with GND adding 100 mV to the output. |
| 7 | 200mV | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating, with GND adding 200 mV to the output. |
| 8 | GND | power_in | Ground pin that must be connected with low impedance to the other GND pin and the exposed pad. |
| 9 | 400mV | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating, with GND adding 400 mV to the output. |
| 10 | 800mV | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating, with GND adding 800 mV to the output. |
| 11 | 1.6V | passive | VOUT programming pin tied to the internal feedback network; connect to GND, SNS or leave floating, with GND adding 1.6 V to the output. |
| 12 | BIAS | power_in | Bias supply pin that reduces power dissipation at low input and output voltages and improves DC and AC performance when VIN ≤ 2.2 V; a 10 µF or greater capacitor to GND is required, and the pin must be left floating or grounded if unused. |
| 13 | NR/SS | passive | Noise reduction and soft-start pin; an external capacitor to GND lowers reference noise and sets the soft-start time, with 10 nF or greater recommended close to the pin. |
| 14 | EN | input | Enable pin: driving it high enables the device and driving it low disables it, with thresholds of 0.4 V maximum (low) and 1.1 V minimum (high); it must be tied to IN or BIAS if enable control is not used. |
| 15 | IN | power_in | Input supply pin with a operating range of 1.1 V to 6.5 V; a 10 µF or greater ceramic capacitor (at least 5 µF) from IN to GND, placed as close to the pin as possible, is required. |
| 16 | IN | power_in | Input supply pin with an operating range of 1.1 V to 6.5 V; connect with the input capacitor placed as close to the pin as possible. |
| 17 | IN | power_in | Input supply pin with an operating range of 1.1 V to 6.5 V; connect with the input capacitor placed as close to the pin as possible. |
| 18 | GND | power_in | Ground pin that must be connected with low impedance to the other GND pin and the exposed pad. |
| 19 | OUT | power_out | Regulated output pin; connect to the 47 µF or greater ceramic output capacitor to GND as close to the pin as possible. |
| 20 | OUT | power_out | Regulated output pin; connect to the 47 µF or greater ceramic output capacitor to GND as close to the pin as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GONGMOSEMI |
| Package | QFN-20-EP(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage range, pin-programmed (GM1203A) | VFB | 0.5 | 3.65 | V | GM1203A, 使用引脚编程 | 9 | |
| Output voltage range, external resistor divider (GM1203A) | VFB | 0.5 | 5.5 | V | GM1203A, 使用外部电阻(2), 不包括外部电阻容差 | 9 | |
| Output voltage accuracy | -1 | 1 | % | 0.5 V ≤ VOUT ≤ 3.65 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 9 | ||
| Output voltage accuracy with BIAS | -1 | 1.3 | % | VIN = 1.1 V, VOUT = 0.5V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 9 | ||
| Output current limit (3A variant, excludes -3-R7 4A row) | ILIM | 3.7 | 4.2 | 6.7 | A | VOUT 外加 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 9 |
| EN pin high-level input voltage | VEN_IH | 1.1 | 6.5 | V | 9 | ||
| EN pin low-level input voltage | VEN_IL | 0 | 0.4 | V | 9 | ||
| EN pin current | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 9 | |
| PG falling threshold | VPG_FALLING | 82 | 91 | 93 | % × VOUT | PG 引脚阈值 下降 | 9 |
| Shutdown ground pin current (typical) | IGND | 18 | µA | 关断, VIN = 6.5 V, VEN = 0.5 V | 9 | ||
| Dropout voltage, 3A, VIN = 1.5 V | VDO | 140 | 260 | mV | VIN = 1.5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3A, VIN = 5.4 V | VDO | 115 | 220 | mV | VIN = 5.4 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| Dropout voltage, 3A, VIN = 1.1 V, VBIAS = 5 V | VDO | 120 | 210 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 3 A, 0.9 × VOUT(nom) | 9 | |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 10 | |
| NR/SS charging current | INR/SS | 4 | 9 | 11.5 | µA | VNR/SS = GND, VIN = 6.5 V | 10 |
| Thermal shutdown threshold (typical) | TSD | 150 | °C | 关断阈值，温度不断上升 | 10 | ||
| Thermal shutdown hysteresis (typical) | TSD_HYS | 20 | °C | 开机阈值，温度不断下降 | 10 | ||
| IN, BIAS, PG, EN to GND voltage | -0.3 | 7 | V | 8 | |||
| SNS, OUT to GND voltage (upper limit printed as VIN+0.3 V) | -0.3 | V | upper limit printed as VIN + 0.3 V | 8 | |||
| NR/SS, FB to GND voltage | -0.3 | 3.6 | V | 8 | |||
| Output-setting pins to GND voltage (upper limit printed as VOUT+0.3 V) | -0.3 | V | upper limit printed as VOUT + 0.3 V | 8 | |||
| PG current | -5 | mA | 8 | ||||
| Storage temperature range | -65 | 150 | °C | 8 | |||
| Operating temperature range (GM1203AACPZ grade) | -40 | 125 | °C | -40°C to +125°C grade per ordering guide (M grade is -55 to +125) | 8 | ||
| Thermal resistance junction-to-ambient, 20-pin 3.5 mm × 3.5 mm QFN | θJA | 43.4 | °C/W | 20-pin 3.5 mm × 3.5 mm QFN, worst case, surface-mount on board | 8 | ||
| Continuous operating junction temperature | TJ | 125 | °C | for reliable continuous operation | 20 | ||
| Input voltage with BIAS applied | VIN | 1.1 | 6.5 | V | VBIAS applied (≥3 V when VIN < 1.5 V) | 18 | |
| Input voltage without BIAS | VIN | 1.5 | 6.5 | V | BIAS floating or grounded | 1 | |
| BIAS supply voltage when VIN < 1.5 V | VBIAS | 3 | V | VIN < 1.5 V | 18 | ||
| Input capacitor, IN to GND | CIN | 10 | µF | ceramic, close to IN pins | 6 | ||
| BIAS capacitor, BIAS to GND | CBIAS | 10 | µF | BIAS pin used | 6 | ||
| Output capacitor, OUT to GND (effective) | COUT | 47 | µF | ceramic, effective capacitance ≥22 µF | 18 |
CAD (KiCad official)
- Symbol:
GM1203AACPZ-1-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: QFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gm1203aacpz-1-r7-etched.step/gm1203aacpz-1-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gm1203aacpz-1-r7.step/gm1203aacpz-1-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GONGMOSEMI datasheet (25 pp, sha256
f744d3090b584d94, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).