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GL3224-ONY04

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Genesys Logic USB Converters, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GL3224-ONY04

Genesys Logic · USB Converters · QFN-48-EP(7x7)

GL3224-ONY04 from Genesys Logic, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD1_CDZ input SD card detect for slot 1 with internal pull-up; 0 = card inserted, 1 = no card.
2 MS1_INS/SD1_WP input Slot 1 input with internal pull-up: SD write protect (0 = write enabled, 1 = write protected) or MS insertion detect (0 = card inserted, 1 = no card).
3 GND power_in Ground.
4 DM bidirectional USB 2.0 D- analog data line.
5 DP bidirectional USB 2.0 D+ analog data line.
6 AVDD33 power_in Analog 3.3V power source.
7 TXN output USB 3.0 SuperSpeed transmit differential negative (analog).
8 TXP output USB 3.0 SuperSpeed transmit differential positive (analog).
9 AVDD12 power_in Analog 1.2V power source.
10 RXN input USB 3.0 SuperSpeed receive differential negative (analog).
11 RXP input USB 3.0 SuperSpeed receive differential positive (analog).
12 GND power_in Ground.
13 X1 input 25 MHz crystal input; can also be driven by an external 25 MHz clock.
14 X2 bidirectional 25 MHz crystal output.
15 AVDD33 power_in Analog 3.3V power source.
16 RTERM passive USB reference resistor; a 680 ohm, 1% resistor is recommended between RTERM and GND.
17 SPI_MISO input SPI interface input, connected to the SPI flash data output.
18 SPI_MOSI output SPI interface output, connected to the SPI flash data input.
19 SPI_CK output SPI interface clock output.
20 SPI_CS output SPI interface chip select output.
21 LED output Memory card access LED output.
22 VBUS power_in 5V power source.
23 S1M1_VCC power_out SD/MS card power for slot 1, switched by on-chip power MOSFET.
24 S2M2_VCC power_out SD/MS card power for slot 2, switched by on-chip power MOSFET.
25 DVDD33 power_in Digital 3.3V power source.
26 DVDD12 power_in Digital 1.2V power source.
27 S2D1_M2BS bidirectional Slot 2 SD data pin; alternate function is MS/MSP bus state output.
28 S2D0_M2D1 bidirectional Slot 2 SD data pin; alternate function is MS/MSP data signal.
29 S2CK_M2D0 output Slot 2 SD clock output; alternate function is MS/MSP data signal.
30 S2CM_M2D2 bidirectional Slot 2 SD command/response with internal pull-up; alternate function is MS/MSP data signal.
31 S2D3_M2D3 bidirectional Slot 2 SD data pin; alternate function is MS/MSP data signal.
32 S2D2_M2CK bidirectional Slot 2 SD data pin; alternate function is MS clock output.
33 VUHS_2 power_in SD 3.0 I/O pad power sourced from the internal regulator; no external power input is needed.
34 DVDD33 power_in Digital 3.3V power source.
35 MS2_INS/SD2_WP input Slot 2 input with internal pull-up: SD write protect (0 = write enabled, 1 = write protected) or MS insertion detect (0 = card inserted, 1 = no card).
36 SD2_CDZ input SD card detect for slot 2 with internal pull-up; 0 = card inserted, 1 = no card.
37 S1D1_M1BS bidirectional Slot 1 SD data pin; alternate function is MS/MSP bus state output.
38 S1D0_M1D1 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
39 S1CK_M1D0 output Slot 1 SD clock output; alternate function is MS/MSP data signal.
40 S1CM_M1D2 bidirectional Slot 1 SD command/response with internal pull-up; alternate function is MS/MSP data signal.
41 S1D3_M1D3 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
42 S1D2_M1CK bidirectional Slot 1 SD data pin; alternate function is MS clock output.
43 VUHS_1 power_in SD 3.0 I/O pad power sourced from the internal regulator; no external power input is needed.
44 DVDD33 power_in Digital 3.3V power source.
45 S1D7_M1D4 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
46 S1D6_M1D5 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
47 S1D5_M1D6 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
48 S1D4_M1D7 bidirectional Slot 1 SD data pin; alternate function is MS/MSP data signal.
49 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Genesys Logic
Package QFN-48-EP(7x7)
Category Interface
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 18
Operating Temperature 0 70 °C 18
Supply Voltage 4.75 5.25 V 18
Oscillator or Crystal Frequency tolerance (FOSC nominal 25 MHz) FOSC -0.03 0.03 % 18
Supply Voltage (DC characteristics) VCC 4.75 5 5.25 V 18
Input Leakage Current II -10 10 µA 0 < VIN < DVDD 18
Input High Voltage VIH 2 V 18
Input Low Voltage VIL 0.4 V 18
Output High Voltage VOH 2.8 V DVDD = 3.3V 18
Output Low Voltage VOL 0.4 V 18
Chip reset sense timing width TRST 2 us 20
AVDD power up to reset de-assert T1 500 us 20
Reset de-assert to respond USB command ready T2 95 ms 20
Reset de-assert to SuperSpeed termination on T3 12 ms 20
SD/MMC clock frequency Identification Mode FID 400 KHz 20
SD clock frequency Default Speed Mode FDS 25 MHz 20
SD clock frequency High Speed Mode FHS 50 MHz 20
MMC clock frequency High Speed Mode FHS 52 MHz 20
SD clock frequency Ultra High Speed Mode: SDR25 FSDR25 50 MHz 20
SD clock frequency Ultra High Speed Mode: DDR50 FDDR50 50 MHz 20
SD clock frequency Ultra High Speed Mode: SDR50 FSDR50 100 MHz 20
SD clock frequency Ultra High Speed Mode: SDR104 FSDR104 208 MHz 20
e•MMC clock frequency Identification Mode FID 400 KHz 21
e•MMC clock frequency High Speed SDR FSDR 52 MHz 21
e•MMC clock frequency High Speed DDR FDDR 52 MHz 21
e•MMC clock frequency HS200 FHS200 200 MHz 21
MS card clock frequency Default Speed Mode FDS 20 MHz 21
MS card clock frequency MS PRO 4bit Mode FMSP 40 MHz 21
MS card clock frequency MS PRO HG 8bit Mode FMSPHG 60 MHz 21

CAD (KiCad official)

  • Symbol: GL3224-ONY04
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: gl3224-ony04-etched.step / gl3224-ony04-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gl3224-ony04.step / gl3224-ony04.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Genesys Logic datasheet (25 pp, sha256 928ab38456ac3f4e, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF