# GD32L233CCT6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

GD32L233CCT6 from GigaDevice Semicon Beijing, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Default function VBAT; the pin table gives no further electrical limit for this pin. |
| 2 | PC13 | bidirectional | Default PC13; alternate EVENTOUT; additional RTC_TAMP0, RTC_OUT, RTC_TS, WKUP1. |
| 3 | PC14-OSC32IN | bidirectional | Default PC14; alternate EVENTOUT; additional OSC32IN. |
| 4 | PC15-OSC32OUT | bidirectional | Default PC15; alternate EVENTOUT; additional OSC32OUT. |
| 5 | PF0-OSCIN | bidirectional | Default OSCIN; alternate EVENTOUT, SPI1_NSS, I2S1_WS; additional PF0. |
| 6 | PF1-OSCOUT | bidirectional | Default OSCOUT; alternate EVENTOUT, SPI1_SCK, I2S1_CK; additional PF1. |
| 7 | NRST | bidirectional | Default NRST reset pin (I/O in the pin table; NRST electrical limits are given in section 4.11). |
| 8 | VSS | power_in | Default function VSS; ground pin. |
| 9 | VREF | power_in | Default function VREF; reference voltage pin. |
| 10 | VDD | power_in | Default function VDD; main supply pin. |
| 11 | PA0 | bidirectional | Default PA0; alternate USART1_CTS, TIMER1_CH0_ETI, CMP0_OUT, EVENTOUT, UART3_TX; additional WKUP0, ADC_IN0, RTC_TAMP1, CMP0_IM4. |
| 12 | PA1 | bidirectional | Default PA1; alternate USART1_RTS, TIMER1_CH1, I2C0_SMBA, SPI0_SCK, EVENTOUT, UART3_RX; additional ADC_IN1, CMP0_IP. |
| 13 | PA2 | bidirectional | Default PA2; alternate USART1_TX, TIMER8_CH0, TIMER1_CH2, SPI0_IO2, CMP1_OUT, LPUART_TX, EVENTOUT; additional ADC_IN2, CMP1_IM4, RTC_TAMP2, WKUP2. |
| 14 | PA3 | bidirectional | Default PA3; alternate USART1_RX, TIMER8_CH1, TIMER1_CH3, SPI0_IO3, LPUART_RX, EVENTOUT; additional ADC_IN3, CMP1_IP0. |
| 15 | PA4 | bidirectional | Default PA4; alternate SPI0_NSS, USART1_CK, SPI1_NSS, I2S1_WS, LPTIMER_OUT, EVENTOUT; additional ADC_IN4, DAC_OUT. |
| 16 | PA5 | bidirectional | Default PA5; alternate SPI0_SCK, TIMER1_CH0_ETI, LPTIMER_ETI0, EVENTOUT; additional ADC_IN5. |
| 17 | PA6 | bidirectional | Default PA6; alternate SPI0_MISO, TIMER2_CH0, LPTIMER_IN0, CMP0_OUT, LPUART_CTS, EVENTOUT; additional ADC_IN6. |
| 18 | PA7 | bidirectional | Default PA7; alternate SPI0_MOSI, TIMER2_CH1, LPTIMER_ETI0, CMP1_OUT, EVENTOUT; additional ADC_IN7. |
| 19 | PB0 | bidirectional | Default PB0; alternate TIMER2_CH2, LPTIMER_OUT, SPI0_NSS, CMP0_OUT, EVENTOUT; additional ADC_IN8, VREF_OUT. |
| 20 | PB1 | bidirectional | Default PB1; alternate TIMER2_CH3, LPUART_RTS, LPTIMER_IN0, EVENTOUT; additional ADC_IN9, VREF_OUT. |
| 21 | BOOT1-PB2 | bidirectional | Default BOOT1; 5 V tolerant (5VT); alternate LPTIMER_OUT, EVENTOUT, RTC_OUT; additional PB2, WKUP3. |
| 22 | PB10 | bidirectional | Default PB10; 5 V tolerant (5VT); alternate SPI1_SCK, I2S1_CK, LPUART_TX, I2C1_SCL, LPUART_RX, TIMER1_CH2, CMP0_OUT, EVENTOUT. |
| 23 | PB11 | bidirectional | Default PB11; 5 V tolerant (5VT); alternate LPUART_RX, I2C1_SDA, LPUART_TX, TIMER1_CH3, CMP1_OUT, EVENTOUT. |
| 24 | PB12 | bidirectional | Default PB12; 5 V tolerant (5VT); alternate SPI1_NSS, I2S1_WS, I2C1_SMBA, LPUART_RTS, EVENTOUT. |
| 25 | PB13 | bidirectional | Default PB13; 5 V tolerant (5VT); alternate CK_OUT, SPI1_SCK, I2S1_CK, LPUART_CTS, I2C1_SCL, EVENTOUT. |
| 26 | PB14 | bidirectional | Default PB14; 5 V tolerant (5VT); alternate SPI1_MISO, LPUART_RTS, I2C1_SDA, TIMER11_CH0 (GD32L233CB/C only), EVENTOUT, RTC_OUT. |
| 27 | PB15 | bidirectional | Default PB15; 5 V tolerant (5VT); alternate SPI1_MOSI, I2S1_SD, TIMER11_CH1 (GD32L233CB/C only), EVENTOUT; additional RTC_REFIN. |
| 28 | PC6 | bidirectional | Default PC6; 5 V tolerant (5VT); alternate I2S1_MCK, TIMER2_CH0, EVENTOUT; additional WKUP4. |
| 29 | PC7 | bidirectional | Default PC7; 5 V tolerant (5VT); alternate TIMER2_CH1, EVENTOUT. |
| 30 | PA8 | bidirectional | Default PA8; 5 V tolerant (5VT); alternate USART0_CK, CK_OUT, LPTIMER_OUT, EVENTOUT, CTC_SYNC; additional VCORE. |
| 31 | PA9 | bidirectional | Default PA9; 5 V tolerant (5VT); alternate CK_OUT, USART0_TX, I2C0_SCL, EVENTOUT, LPTIMER_IN1. |
| 32 | PA10 | bidirectional | Default PA10; 5 V tolerant (5VT); alternate USART0_RX, I2C0_SDA, EVENTOUT. |
| 33 | PA11 | bidirectional | Default PA11; 5 V tolerant (5VT); alternate CMP0_OUT, USART0_CTS, SPI0_MISO, EVENTOUT; additional USBDM. |
| 34 | PA12 | bidirectional | Default PA12; 5 V tolerant (5VT); alternate CMP1_OUT, USART0_RTS, SPI0_MOSI, EVENTOUT; additional USBDP. |
| 35 | PA13 | bidirectional | Default SWDIO; 5 V tolerant (5VT); alternate LPUART_RX, I2C0_SCL, USART0_TX, SPI0_IO2, SPI0_NSS, EVENTOUT; additional PA13. |
| 36 | PA14 | bidirectional | Default SWCLK; 5 V tolerant (5VT); alternate LPUART_TX, USART1_TX, I2C0_SDA, USART0_RX, SPI0_IO3, SPI1_NSS, I2S1_WS, EVENTOUT; additional PA14. |
| 37 | PA15 | bidirectional | Default PA15; 5 V tolerant (5VT); alternate SPI1_NSS, I2S1_WS, TIMER1_CH0_ETI, SPI0_NSS, USART1_RX, EVENTOUT. |
| 38 | PC10 | bidirectional | Default PC10; 5 V tolerant (5VT); alternate UART3_TX, LPUART_TX, SPI1_SCK, I2S1_CK, EVENTOUT. |
| 39 | PC11 | bidirectional | Default PC11; 5 V tolerant (5VT); alternate UART3_RX, LPUART_RX, SPI1_MISO, EVENTOUT. |
| 40 | PC12 | bidirectional | Default PC12; 5 V tolerant (5VT); alternate UART4_TX (GD32L233CB/C only), SPI1_MOSI, I2S1_SD, EVENTOUT. |
| 41 | PB3 | bidirectional | Default PB3; 5 V tolerant (5VT); alternate UART4_TX (GD32L233CB/C only), SPI1_SCK, I2S1_CK, TIMER1_CH1, SPI0_SCK, USART0_RTS, EVENTOUT, LPTIMER_IN1; additional CMP1_IM6. |
| 42 | PB4 | bidirectional | Default PB4; 5 V tolerant (5VT); alternate UART4_RX (GD32L233CB/C only), SPI1_MISO, TIMER2_CH0, SPI0_MISO, USART0_CTS, EVENTOUT; additional CMP1_IP1. |
| 43 | PB5 | bidirectional | Default PB5; alternate LPTIMER_IN0, I2C0_SMBA, SPI1_MOSI, I2S1_SD, TIMER2_CH1, SPI0_MOSI, USART0_CK, CMP1_OUT, EVENTOUT; additional CMP1_IP2 (no 5VT marking in the pin table). |
| 44 | PB6 | bidirectional | Default PB6; 5 V tolerant (5VT); alternate LPTIMER_ETI0, I2C1_SCL, I2C0_SCL, USART0_TX, SPI0_IO2, EVENTOUT; additional CMP1_IP3. |
| 45 | PB7 | bidirectional | Default PB7; 5 V tolerant (5VT); alternate I2C1_SDA, I2C0_SDA, USART0_RX, SPI0_IO3, EVENTOUT; additional CMP1_IP4. |
| 46 | BOOT0-PD3 | bidirectional | Default BOOT0; alternate USART1_CTS, SPI1_MISO, I2S1_MCK; additional PD3 (no 5VT marking in the pin table). |
| 47 | PB8 | bidirectional | Default PB8; 5 V tolerant (5VT); alternate I2C1_SCL, I2C0_SCL, CMP0_OUT, EVENTOUT. |
| 48 | PB9 | bidirectional | Default PB9; 5 V tolerant (5VT); alternate I2C1_SDA, SPI1_NSS, I2S1_WS, I2C0_SDA, CMP1_OUT, EVENTOUT. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on other I/O (absolute maximum) | VIN |  |  | 3.63 | V |  | 50 |
| Input voltage on 5V tolerant pin (absolute maximum) | VIN |  |  | 5.5 | V |  | 50 |
| Variations between different VDD power pins | /ΔVDDx/ |  |  | 50 | mV |  | 50 |
| Variations between different ground pins | /VSSX −VSS/ |  |  | 50 | mV |  | 50 |
| Maximum current for GPIO pins | IIO | -25 |  | 25 | mA |  | 50 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 50 |
| Power dissipation of LQFP48 | PD |  |  | 574 | mW | TA = 85°C, LQFP48 | 50 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 50 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 50 |
| Supply voltage | VDD | 1.71 | 3.3 | 3.63 | V |  | 50 |
| Analog supply voltage | VDDA | 1.71 | 3.3 | 3.63 | V |  | 50 |
| Battery supply voltage | VBAT | 1.71 | 3.3 | 3.63 | V |  | 50 |
| AHB1 clock frequency | fHCLK1 | 0 |  | 64 | MHz |  | 51 |
| AHB2 clock frequency | fHCLK2 | 0 |  | 64 | MHz |  | 51 |
| APB1 clock frequency | fAPB1 | 0 |  | 32 | MHz |  | 51 |
| APB2 clock frequency | fAPB2 | 0 |  | 64 | MHz |  | 51 |
| Power on reset threshold | VPOR | 1.56 | 1.6 | 1.63 | V |  | 60 |
| Power down reset threshold | VPDR | 1.52 | 1.56 | 1.59 | V |  | 60 |
| Electrostatic discharge voltage (human body model) | VESD(HBM) |  |  | 2000 | V | JS-001-2017 | 61 |
| Electrostatic discharge voltage (charge device model) | VESD(CDM) |  |  | 500 | V | JS-002-2018 | 61 |
| Static latch-up I-test | LU | -200 |  | 200 | mA | JESD78 | 61 |
| Static latch-up supply overvoltage |  |  |  | 5.4 | V |  | 61 |
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 8 | 48 | MHz | VDD = 3.3 V | 61 |
| Crystal or ceramic duty cycle (HXTAL) | Ducy(HXTAL) | 30 | 50 | 70 | % |  | 61 |
| Recommended matching capacitance on OSCIN and OSCOUT | CHXTAL |  | 20 | 30 | pF |  | 61 |
| External clock source or oscillator frequency (HXTAL bypass) | fHXTAL_ext | 1 | 8 | 50 | MHz | VDD = 3.3 V | 62 |
| OSCIN high or low time (HXTAL bypass) | tH/L(HXTAL) | 5 |  |  | ns |  | 62 |
| OSCIN rise or fall time (HXTAL bypass) | tR/F(HXTAL) |  |  | 10 | ns |  | 62 |
| Crystal or ceramic duty cycle (LXTAL) | Ducy(LXTAL) | 30 |  | 70 | % |  | 62 |
| External clock source or oscillator frequency (LXTAL bypass) | fLXTAL_ext |  | 32.768 | 1000 | kHz | VDD = 3.3 V | 63 |
| OSC32IN high or low time (LXTAL bypass) | tH/L(LXTAL) | 250 |  |  | ns |  | 63 |
| OSC32IN rise or fall time (LXTAL bypass) | tR/F(LXTAL) |  |  | 50 | ns |  | 63 |
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1.5 |  | 1.5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 63 |
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1 |  | 1 | % | VDD = VDDA = 3.3 V | 63 |
| IRC16M oscillator duty cycle | DIRC16M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 63 |
| Low speed internal oscillator (IRC32K) frequency | fIRC32K | 31.7 |  | 32.3 | kHz | VDD = VDDA = 3.3 V, TA = -40~85 °C | 64 |
| Low speed internal oscillator (IRC32K) frequency | fIRC32K | 30 |  | 35 | kHz | VDD = VDDA = 3.3 V | 64 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -3.3 |  | -0.25 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 64 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -2 |  | 2 | % | VDD = VDDA = 3.3 V | 64 |
| PLL input clock frequency | fPLLIN | 2 |  | 16 | MHz |  | 65 |
| PLL output clock frequency | fPLLOUT | 16 |  | 64 | MHz |  | 65 |
| PLL VCO output clock frequency | fVCO |  |  | 64 | MHz |  | 65 |
| PLL lock time | tLOCK |  |  | 200 | μs |  | 65 |
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 10 |  |  | kcycles | TA = -40 °C ~ +85 °C | 65 |
| Data retention time | tRET | 10 |  |  | years | 10k cycles at TA = 85 °C | 65 |
| Analog Supply Voltage (VREF buffer) | VDDA | 2.7 | 3.3 | 3.63 | V |  | 66 |
| Output Reference Voltage | VREF | 2.49 | 2.5 | 2.51 | V | VDDA = 3.3 V | 66 |
| Output Reference Voltage | VREF | 2.47 | 2.5 | 2.53 | V | All VDDA, All Temp | 66 |
| VREF buffer setup time | TSU |  |  | 200 | μs | CL = 1 μF + 10 nF | 66 |
| ADC operating voltage | VDDA | 1.8 | 3.3 | 3.6 | V |  | 69 |
| ADC clock | fADC | 0.125 |  | 16 | MHz |  | 69 |
| Sampling time | ts | 0.156 |  | 14.97 | μs | fADC = 16 MHz | 69 |
| External input impedance (ADC RAIN) | RAIN |  |  | 513.6 | kΩ | See Equation 1 | 69 |
| Temp Sensor Error Using Typical Slope and Factory-Calibrated Offset | ETOT | -3.5 |  | 4.7 | °C | TA = -40 °C to 85 °C | 72 |
| CMP operating voltage | VDDA | 1.71 | 3.3 | 3.63 | V |  | 73 |
| Timer resolution time | tres | 15.6 |  |  | ns | fTIMERxCLK = 64 MHz | 74 |
| SLCD external voltage | VSLCD |  |  | 3.63 | V |  | 75 |
| Thermal resistance, junction-to-ambient (LQFP48) | θJA |  | 69.64 |  | °C/W | Natural convection, 2S2P PCB | 92 |
| Thermal resistance, junction-to-board (LQFP48) | θJB |  | 43.16 |  | °C/W | Cold plate, 2S2P PCB | 92 |
| Thermal resistance, junction-to-case (LQFP48) | θJC |  | 25.36 |  | °C/W | Cold plate, 2S2P PCB | 93 |

## CAD (KiCad official)

- Symbol: `GD32L233CCT6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `gd32l233cct6-etched.step` / `gd32l233cct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32l233cct6.step` / `gd32l233cct6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836319301410816) (96 pp, sha256 `377d085560ed5b0e`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32l233cct6-datasheet.pdf)