component
GD32F470ZKT6
Public Made by Adomby adom
GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownGD32F470ZKT6
GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)
GD32F470ZKT6 from GigaDevice Semicon Beijing, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | Default PE2; alternate SPI3_SCK, ENET_MII_TXD3, EXMC_A23, EVENTOUT; 5 V tolerant I/O. |
| 2 | PE3 | bidirectional | Default PE3; alternate EXMC_A19, EVENTOUT; 5 V tolerant I/O. |
| 3 | PE4 | bidirectional | Default PE4; alternate SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT; 5 V tolerant I/O. |
| 4 | PE5 | bidirectional | Default PE5; alternate TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT; 5 V tolerant I/O. |
| 5 | PE6 | bidirectional | Default PE6; alternate TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT; 5 V tolerant I/O. |
| 6 | VBAT | power_in | Default function VBAT; the block diagram labels the backup-powered domain as powered by VBAT. |
| 7 | PC13-TAMPER-RTC | bidirectional | Default PC13; additional RTC_TAMP0, RTC_OUT, RTC_TS; alternate EVENTOUT; 5 V tolerant I/O. |
| 8 | PC14-OSC32IN | bidirectional | Default PC14; additional OSC32IN; alternate EVENTOUT; 5 V tolerant I/O. |
| 9 | PC15-OSC32OUT | bidirectional | Default PC15; additional OSC32OUT; alternate EVENTOUT; 5 V tolerant I/O. |
| 10 | PF0 | bidirectional | Default PF0; alternate I2C1_SDA, EXMC_A0, EVENTOUT, CTC_SYNC; 5 V tolerant I/O. |
| 11 | PF1 | bidirectional | Default PF1; alternate I2C1_SCL, EXMC_A1, EVENTOUT; 5 V tolerant I/O. |
| 12 | PF2 | bidirectional | Default PF2; alternate I2C1_SMBA, EXMC_A2, EVENTOUT; 5 V tolerant I/O. |
| 13 | PF3 | bidirectional | Default PF3; alternate EXMC_A3, EVENTOUT, I2C1_TXFRAME; additional ADC2_IN9; 5 V tolerant I/O. |
| 14 | PF4 | bidirectional | Default PF4; alternate EXMC_A4, EVENTOUT; additional ADC2_IN14; 5 V tolerant I/O. |
| 15 | PF5 | bidirectional | Default PF5; alternate EXMC_A5, EVENTOUT; additional ADC2_IN15; 5 V tolerant I/O. |
| 16 | VSS | power_in | Ground pin (default function VSS). |
| 17 | VDD | power_in | Digital power supply pin (default function VDD). |
| 18 | PF6 | bidirectional | Default PF6; alternate TIMER9_CH0, SPI4_NSS, UART6_RX, EXMC_NIORD, EVENTOUT; additional ADC2_IN4; 5 V tolerant I/O. |
| 19 | PF7 | bidirectional | Default PF7; alternate TIMER10_CH0, SPI4_SCK, UART6_TX, EXMC_NREG, EVENTOUT; additional ADC2_IN5; 5 V tolerant I/O. |
| 20 | PF8 | bidirectional | Default PF8; alternate SPI4_MISO, TIMER12_CH0, EXMC_NIOWR, EVENTOUT; additional ADC2_IN6; 5 V tolerant I/O. |
| 21 | PF9 | bidirectional | Default PF9; alternate SPI4_MOSI, TIMER13_CH0, EXMC_CD, EVENTOUT; additional ADC2_IN7; 5 V tolerant I/O. |
| 22 | PF10 | bidirectional | Default PF10; alternate EXMC_INTR, DCI_D11, TLI_DE, EVENTOUT; additional ADC2_IN8; 5 V tolerant I/O. |
| 23 | PH0 | bidirectional | Default PH0, OSCIN; additional OSCIN; alternate EVENTOUT; 5 V tolerant I/O. |
| 24 | PH1 | bidirectional | Default PH1, OSCOUT; additional OSCOUT; alternate EVENTOUT; 5 V tolerant I/O. |
| 25 | NRST | input | Default NRST reset pin; external circuit is shown in Figure 4-5 and NRST electrical limits are in Section 4.11. |
| 26 | PC0 | bidirectional | Default PC0; alternate USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT; additional ADC012_IN10; 5 V tolerant I/O. |
| 27 | PC1 | bidirectional | Default PC1; alternate SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ENET_MDC, EVENTOUT; additional ADC012_IN11; 5 V tolerant I/O. |
| 28 | PC2 | bidirectional | Default PC2; alternate SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ENET_MII_TXD2, EXMC_SDNE0, EVENTOUT; additional ADC012_IN12; 5 V tolerant I/O. |
| 29 | PC3 | bidirectional | Default PC3; alternate SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ENET_MII_TX_CLK, EXMC_SDCKE0, EVENTOUT; additional ADC012_IN13; 5 V tolerant I/O. |
| 30 | VDD | power_in | Digital power supply pin (default function VDD). |
| 31 | VSSA | power_in | Analog ground pin (default function VSSA). |
| 32 | VREFP | power_in | Positive reference voltage pin (default function VREF+) for the ADC/DAC. |
| 33 | VDDA | power_in | Analog supply pin (default function VDDA). |
| 34 | PA0-WKUP | bidirectional | Default PA0; alternate TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ENET_MII_CRS, EVENTOUT; additional ADC012_IN0 and WKUP; 5 V tolerant I/O. |
| 35 | PA1 | bidirectional | Default PA1; alternate TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX, ENET_MII_RX_CLK, ENET_RMII_REF_CLK, EVENTOUT; additional ADC012_IN1; 5 V tolerant I/O. |
| 36 | PA2 | bidirectional | Default PA2; alternate TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ENET_MDIO, EVENTOUT; additional ADC012_IN2; 5 V tolerant I/O. |
| 37 | PA3 | bidirectional | Default PA3; alternate TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, ENET_MII_COL, TLI_B5, EVENTOUT; additional ADC012_IN3; 5 V tolerant I/O. |
| 38 | VSS | power_in | Ground pin (default function VSS). |
| 39 | VDD | power_in | Digital power supply pin (default function VDD). |
| 40 | PA4 | bidirectional | Default PA4; alternate SPI0_NSS, SPI2_NSS/I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, TLI_VSYNC, EVENTOUT; additional ADC01_IN4 and DAC_OUT0; I/O level not stated as 5 V tolerant in the pin table. |
| 41 | PA5 | bidirectional | Default PA5; alternate TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT; additional ADC01_IN5 and DAC_OUT1; I/O level not stated as 5 V tolerant in the pin table. |
| 42 | PA6 | bidirectional | Default PA6; alternate TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2, EVENTOUT; additional ADC01_IN6; 5 V tolerant I/O. |
| 43 | PA7 | bidirectional | Default PA7; alternate TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, ENET_MII_RX_DV, ENET_RMII_CRS_DV, EXMC_SDNWE, EVENTOUT; additional ADC01_IN7; 5 V tolerant I/O. |
| 44 | PC4 | bidirectional | Default PC4; alternate ENET_MII_RXD0, ENET_RMII_RXD0, EXMC_SDNE0, EVENTOUT; additional ADC01_IN14; 5 V tolerant I/O. |
| 45 | PC5 | bidirectional | Default PC5; alternate USART2_RX, ENET_MII_RXD1, ENET_RMII_RXD1, EXMC_SDCKE0, EVENTOUT; additional ADC01_IN15; 5 V tolerant I/O. |
| 46 | PB0 | bidirectional | Default PB0; alternate TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1, ENET_MII_RXD2, SDIO_D1, EVENTOUT; additional ADC01_IN8 and IREF; 5 V tolerant I/O. |
| 47 | PB1 | bidirectional | Default PB1; alternate TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ENET_MII_RXD3, SDIO_D2, EVENTOUT; additional ADC01_IN9; 5 V tolerant I/O. |
| 48 | PB2 | bidirectional | Default PB2, BOOT1; alternate TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT; 5 V tolerant I/O. |
| 49 | PF11 | bidirectional | Default PF11; alternate SPI4_MOSI, EXMC_SDNRAS, DCI_D12, EVENTOUT; 5 V tolerant I/O. |
| 50 | PF12 | bidirectional | Default PF12; alternate EXMC_A6, EVENTOUT; 5 V tolerant I/O. |
| 51 | VSS | power_in | Ground pin (default function VSS). |
| 52 | VDD | power_in | Digital power supply pin (default function VDD). |
| 53 | PF13 | bidirectional | Default PF13; alternate EXMC_A7, EVENTOUT; 5 V tolerant I/O. |
| 54 | PF14 | bidirectional | Default PF14; alternate EXMC_A8, EVENTOUT; 5 V tolerant I/O. |
| 55 | PF15 | bidirectional | Default PF15; alternate EXMC_A9, EVENTOUT; 5 V tolerant I/O. |
| 56 | PG0 | bidirectional | Default PG0; alternate EXMC_A10, EVENTOUT; 5 V tolerant I/O. |
| 57 | PG1 | bidirectional | Default PG1; alternate EXMC_A11, EVENTOUT; 5 V tolerant I/O. |
| 58 | PE7 | bidirectional | Default PE7; alternate TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT; 5 V tolerant I/O. |
| 59 | PE8 | bidirectional | Default PE8; alternate TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT; 5 V tolerant I/O. |
| 60 | PE9 | bidirectional | Default PE9; alternate TIMER0_CH0, EXMC_D6, EVENTOUT; 5 V tolerant I/O. |
| 61 | VSS | power_in | Ground pin (default function VSS). |
| 62 | VDD | power_in | Digital power supply pin (default function VDD). |
| 63 | PE10 | bidirectional | Default PE10; alternate TIMER0_CH1_ON, EXMC_D7, EVENTOUT; 5 V tolerant I/O. |
| 64 | PE11 | bidirectional | Default PE11; alternate TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3, EVENTOUT; 5 V tolerant I/O. |
| 65 | PE12 | bidirectional | Default PE12; alternate TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4, EVENTOUT; 5 V tolerant I/O. |
| 66 | PE13 | bidirectional | Default PE13; alternate TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE, EVENTOUT; 5 V tolerant I/O. |
| 67 | PE14 | bidirectional | Default PE14; alternate TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11, TLI_PIXCLK, EVENTOUT; 5 V tolerant I/O. |
| 68 | PE15 | bidirectional | Default PE15; alternate TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT; 5 V tolerant I/O. |
| 69 | PB10 | bidirectional | Default PB10; alternate TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, ENET_MII_RX_ER, SDIO_D7, TLI_G4, EVENTOUT; 5 V tolerant I/O. |
| 70 | PB11 | bidirectional | Default PB11; alternate TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, ENET_MII_TX_EN, ENET_RMII_TX_EN, TLI_G5, EVENTOUT; 5 V tolerant I/O. |
| 71 | NC | unconnected | Not connected (NC) per the LQFP144 pin table. |
| 72 | VDD | power_in | Digital power supply pin (default function VDD). |
| 73 | PB12 | bidirectional | Default PB12; alternate TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ENET_MII_TXD0, ENET_RMII_TXD0, USBHS_ID, EVENTOUT; 5 V tolerant I/O. |
| 74 | PB13 | bidirectional | Default PB13; alternate TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ENET_MII_TXD1, ENET_RMII_TXD1, EVENTOUT, I2C1_TXFRAME; additional USBHS_VBUS; 5 V tolerant I/O. |
| 75 | PB14 | bidirectional | Default PB14; alternate TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT; 5 V tolerant I/O. |
| 76 | PB15 | bidirectional | Default PB15; alternate RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT; 5 V tolerant I/O. |
| 77 | PD8 | bidirectional | Default PD8; alternate USART2_TX, EXMC_D13, EVENTOUT; 5 V tolerant I/O. |
| 78 | PD9 | bidirectional | Default PD9; alternate USART2_RX, EXMC_D14, EVENTOUT; 5 V tolerant I/O. |
| 79 | PD10 | bidirectional | Default PD10; alternate USART2_CK, EXMC_D15, TLI_B3, EVENTOUT; 5 V tolerant I/O. |
| 80 | PD11 | bidirectional | Default PD11; alternate USART2_CTS, EXMC_A16, EVENTOUT; 5 V tolerant I/O. |
| 81 | PD12 | bidirectional | Default PD12; alternate TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT; 5 V tolerant I/O. |
| 82 | PD13 | bidirectional | Default PD13; alternate TIMER3_CH1, EXMC_A18, EVENTOUT; 5 V tolerant I/O. |
| 83 | VSS | power_in | Ground pin (default function VSS). |
| 84 | VDD | power_in | Digital power supply pin (default function VDD). |
| 85 | PD14 | bidirectional | Default PD14; alternate TIMER3_CH2, EXMC_D0, EVENTOUT; 5 V tolerant I/O. |
| 86 | PD15 | bidirectional | Default PD15; alternate TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC; 5 V tolerant I/O. |
| 87 | PG2 | bidirectional | Default PG2; alternate EXMC_A12, EVENTOUT; 5 V tolerant I/O. |
| 88 | PG3 | bidirectional | Default PG3; alternate EXMC_A13, EVENTOUT; 5 V tolerant I/O. |
| 89 | PG4 | bidirectional | Default PG4; alternate EXMC_A14, EVENTOUT; 5 V tolerant I/O. |
| 90 | PG5 | bidirectional | Default PG5; alternate EXMC_A15, EVENTOUT; 5 V tolerant I/O. |
| 91 | PG6 | bidirectional | Default PG6; alternate EXMC_INT1, DCI_D12, TLI_R7, EVENTOUT; 5 V tolerant I/O. |
| 92 | PG7 | bidirectional | Default PG7; alternate USART5_CK, EXMC_INT2, DCI_D13, TLI_PIXCLK, EVENTOUT; 5 V tolerant I/O. |
| 93 | PG8 | bidirectional | Default PG8; alternate SPI5_NSS, USART5_RTS, ENET_PPS_OUT, EXMC_SDCLK, EVENTOUT; 5 V tolerant I/O. |
| 94 | VSS | power_in | Ground pin (default function VSS). |
| 95 | VDD | power_in | Digital power supply pin (default function VDD). |
| 96 | PC6 | bidirectional | Default PC6; alternate TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT; 5 V tolerant I/O. |
| 97 | PC7 | bidirectional | Default PC7; alternate TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT; 5 V tolerant I/O. |
| 98 | PC8 | bidirectional | Default PC8; alternate TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT; 5 V tolerant I/O. |
| 99 | PC9 | bidirectional | Default PC9; alternate CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT; 5 V tolerant I/O. |
| 100 | PA8 | bidirectional | Default PA8; alternate CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC; 5 V tolerant I/O. |
| 101 | PA9 | bidirectional | Default PA9; alternate TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT; additional USBFS_VBUS; 5 V tolerant I/O. |
| 102 | PA10 | bidirectional | Default PA10; alternate TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME; 5 V tolerant I/O. |
| 103 | PA11 | bidirectional | Default PA11; alternate TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT; 5 V tolerant I/O. |
| 104 | PA12 | bidirectional | Default PA12; alternate TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT; 5 V tolerant I/O. |
| 105 | PA13 | bidirectional | Default JTMS, SWDIO, PA13; alternate EVENTOUT; 5 V tolerant I/O. |
| 106 | NC | unconnected | Not connected (NC) per the LQFP144 pin table. |
| 107 | VSS | power_in | Ground pin (default function VSS). |
| 108 | VDD | power_in | Digital power supply pin (default function VDD). |
| 109 | PA14 | bidirectional | Default JTCK, SWCLK, PA14; alternate EVENTOUT; 5 V tolerant I/O. |
| 110 | PA15 | bidirectional | Default JTDI, PA15; alternate TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS/I2S2_WS, USART0_TX, EVENTOUT; 5 V tolerant I/O. |
| 111 | PC10 | bidirectional | Default PC10; alternate SPI2_SCK/I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, TLI_R2, EVENTOUT; 5 V tolerant I/O. |
| 112 | PC11 | bidirectional | Default PC11; alternate I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT; 5 V tolerant I/O. |
| 113 | PC12 | bidirectional | Default PC12; alternate I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT; 5 V tolerant I/O. |
| 114 | PD0 | bidirectional | Default PD0; alternate SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT; 5 V tolerant I/O. |
| 115 | PD1 | bidirectional | Default PD1; alternate SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT; 5 V tolerant I/O. |
| 116 | PD2 | bidirectional | Default PD2; alternate TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT; 5 V tolerant I/O. |
| 117 | PD3 | bidirectional | Default PD3; alternate SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT; 5 V tolerant I/O. |
| 118 | PD4 | bidirectional | Default PD4; alternate USART1_RTS, EXMC_NOE, EVENTOUT; 5 V tolerant I/O. |
| 119 | PD5 | bidirectional | Default PD5; alternate USART1_TX, EXMC_NWE, EVENTOUT; 5 V tolerant I/O. |
| 120 | VSS | power_in | Ground pin (default function VSS). |
| 121 | VDD | power_in | Digital power supply pin (default function VDD). |
| 122 | PD6 | bidirectional | Default PD6; alternate SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT; 5 V tolerant I/O. |
| 123 | PD7 | bidirectional | Default PD7; alternate USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT; 5 V tolerant I/O. |
| 124 | PG9 | bidirectional | Default PG9; alternate USART5_RX, EXMC_NE1, EXMC_NCE2, DCI_VSYNC, EVENTOUT; 5 V tolerant I/O. |
| 125 | PG10 | bidirectional | Default PG10; alternate SPI5_IO2, TLI_G3, EXMC_NCE3_0, EXMC_NE2, DCI_D2, TLI_B2, EVENTOUT; 5 V tolerant I/O. |
| 126 | PG11 | bidirectional | Default PG11; alternate SPI5_IO3, SPI3_SCK, ENET_MII_TX_EN, ENET_RMII_TX_EN, EXMC_NCE3_1, DCI_D3, TLI_B3, EVENTOUT; 5 V tolerant I/O. |
| 127 | PG12 | bidirectional | Default PG12; alternate SPI5_MISO, SPI3_MISO, USART5_RTS, TLI_B4, EXMC_NE3, TLI_B1, EVENTOUT; 5 V tolerant I/O. |
| 128 | PG13 | bidirectional | Default PG13; alternate SPI5_SCK, SPI3_MOSI, USART5_CTS, ENET_MII_TXD0, ENET_RMII_TXD0, EXMC_A24, EVENTOUT; 5 V tolerant I/O. |
| 129 | PG14 | bidirectional | Default PG14; alternate SPI5_MOSI, SPI3_NSS, USART5_TX, ENET_MII_TXD1, ENET_RMII_TXD1, EXMC_A25, EVENTOUT; 5 V tolerant I/O. |
| 130 | VSS | power_in | Ground pin (default function VSS). |
| 131 | VDD | power_in | Digital power supply pin (default function VDD). |
| 132 | PG15 | bidirectional | Default PG15; alternate USART5_CTS, EXMC_SDNCAS, DCI_D13, EVENTOUT; 5 V tolerant I/O. |
| 133 | PB3 | bidirectional | Default JTDO, PB3; alternate TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK/I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT; 5 V tolerant I/O. |
| 134 | PB4 | bidirectional | Default NJTRST, PB4; alternate TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME; 5 V tolerant I/O. |
| 135 | PB5 | bidirectional | Default PB5; alternate TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI/I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ENET_PPS_OUT, EXMC_SDCKE1, DCI_D10, EVENTOUT; 5 V tolerant I/O. |
| 136 | PB6 | bidirectional | Default PB6; alternate TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, EXMC_SDNE1, DCI_D5, EVENTOUT; 5 V tolerant I/O. |
| 137 | PB7 | bidirectional | Default PB7; alternate TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL, DCI_VSYNC, EVENTOUT; 5 V tolerant I/O. |
| 138 | BOOT0 | bidirectional | Default BOOT0 pin; the pin table classifies it as I/O with 5 V tolerant level. |
| 139 | PB8 | bidirectional | Default PB8; alternate TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, SPI4_MOSI, CAN0_RX, ENET_MII_TXD3, SDIO_D4, DCI_D6, TLI_B6, EVENTOUT; 5 V tolerant I/O. |
| 140 | PB9 | bidirectional | Default PB9; alternate TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7, EVENTOUT; 5 V tolerant I/O. |
| 141 | PE0 | bidirectional | Default PE0; alternate TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT; 5 V tolerant I/O. |
| 142 | PE1 | bidirectional | Default PE1; alternate TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT; 5 V tolerant I/O. |
| 143 | PDR_ON | power_in | Default function PDR_ON; the datasheet gives a recommended PDR_ON pin circuit (Figure 4-4). |
| 144 | VDD | power_in | Digital power supply pin (default function VDD). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External voltage range | VDD | -0.3 | 3.6 | V | Printed as VSS - 0.3 to VSS + 3.6 (relative to VSS) | 72 | |
| External analog supply voltage | VDDA | -0.3 | 3.6 | V | Printed as VSSA - 0.3 to VSSA + 3.6 (relative to VSSA) | 72 | |
| External battery supply voltage | VBAT | -0.3 | 3.6 | V | Printed as VSS - 0.3 to VSS + 3.6 (relative to VSS) | 72 | |
| Input voltage on 5V tolerant pin | VIN | -0.3 | V | Max printed as VDD + 3.6; VIN maximum cannot exceed 5.5 V (note 3) | 72 | ||
| Input voltage on other I/O | VIN | -0.3 | 3.6 | V | Printed min VSS - 0.3 | 72 | |
| Variations between different VDD power pins | /ΔVDDX/ | 50 | mV | 72 | |||
| Variations between different ground pins | /VSSX −VSS/ | 50 | mV | 72 | |||
| Maximum current for GPIO pins | IIO | -25 | 25 | mA | 72 | ||
| Operating temperature range | TA | -40 | 85 | °C | 72 | ||
| Power dissipation at TA = 85°C of LQFP144 | PD | 820 | mW | TA = 85°C, LQFP144 package | 72 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 72 | ||
| Maximum junction temperature | TJ | 125 | °C | 72 | |||
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V | 72 | |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 72 |
| Battery supply voltage | VBAT | 1.8 | 3.6 | V | 72 | ||
| USBHS operating voltage | VDD | 3 | 3.6 | V | USBHS interface | 103 | |
| AHB clock frequency | fHCLK | 240 | MHz | 73 | |||
| APB1 clock frequency | fAPB1 | 60 | MHz | 73 | |||
| APB2 clock frequency | fAPB2 | 120 | MHz | 73 | |||
| fHCLK value to guarantee proper operation of USBHS interface | fHCLK | 30 | MHz | USBHS interface | 103 | ||
| VDD rise time rate | tVDD | 0 | μs/V | Max printed as ∞ | 73 | ||
| VDD fall time rate | tVDD | 20 | μs/V | Max printed as ∞ | 73 | ||
| Electrostatic discharge voltage (human body model) | VESD(HBM) | 5000 | V | TA = 25 °C; JS-001-2017 | 83 | ||
| Electrostatic discharge voltage (charge device model) | VESD(CDM) | 1000 | V | TA = 25 °C; JS-002-2018 | 83 | ||
| Static latch-up I-test | LU | -200 | 200 | mA | TA = 105 °C; JESD78 | 83 | |
| Vsupply over voltage | 5.4 | V | 83 | ||||
| Crystal or ceramic frequency | fHXTAL | 4 | 25 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 83 |
| Recommended matching capacitance on OSCIN and OSCOUT | CHXTAL | 20 | 30 | pF | 83 | ||
| Crystal or ceramic duty cycle | Ducy(HXTAL) | 30 | 50 | 70 | % | 83 | |
| External clock source or oscillator frequency (HXTAL bypass) | fHXTAL_ext | 1 | 50 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 84 | |
| OSCIN high or low time | tH/L(HXTAL) | 5 | ns | 84 | |||
| OSCIN rise or fall time | tR/F(HXTAL) | 10 | ns | 84 | |||
| Duty cycle (HXTAL bypass) | Ducy(HXTAL) | 40 | 60 | % | 84 | ||
| Duty cycle (LXTAL bypass) | Ducy(LXTAL) | 30 | 50 | 70 | % | 85 | |
| External clock source or oscillator frequency (LXTAL bypass) | fLXTAL_ext | 32.768 | 1000 | kHz | VDD = 3.3 V | 85 | |
| OSC32IN high or low time | tH/L(LXTAL) | 450 | ns | 85 | |||
| OSC32IN rise or fall time | tR/F(LXTAL) | 50 | ns | 85 | |||
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1.73 | 1.1 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 86 | |
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1 | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 86 | |
| IRC16M oscillator duty cycle | DucyIRC16M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 86 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -1.31 | 0.39 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 86 | |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -2 | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 86 | |
| IRC48M oscillator duty cycle | DIRC48M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 86 |
| PLL input clock frequency | fPLLIN | 1 | 4 | MHz | 87 | ||
| PLL output clock frequency | fPLLOUT | 100 | 500 | MHz | 87 | ||
| PLL VCO output clock frequency | fVCO | 32 | 344 | MHz | 87 | ||
| PLL lock time | tLOCK | 400 | μs | 87 | |||
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 50 | kcycles | TA = -40 °C ~ +85 °C | 89 | ||
| Word programming time | tPROG | 37.5 | 180 | μs | TA = -40°C ~ +85°C | 89 | |
| Sector(16kB) erase time | tERASE16kB | 200 | 2000 | ms | TA = -40°C ~ +85°C | 89 | |
| Sector(64kB) erase time | tERASE64kB | 300 | 4000 | ms | 89 | ||
| Sector(128kB) erase time | tERASE128kB | 600 | 8000 | ms | 89 | ||
| Mass erase time (3MB) | tMERASE(3MB) | 14.4 | 192 | s | TA = -40°C ~ +85°C | 89 | |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL | 0.1 | V | IIO = +8 mA, VDD = 3.3 V | 90 | ||
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 3.18 | V | IIO = +8 mA, VDD = 3.3 V | 90 | ||
| TRise/TFall (IO_Speed level 3) | TRise/TFall | 2.8 | ns | OSPD = 11 (IO_Speed level 3), 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF | 92 | ||
| ADC clock | fADC | 0.1 | 40 | MHz | 93 | ||
| Sampling time | ts | 0.075 | 12 | μs | fADC = 40 MHz | 93 | |
| Startup time | tSU | 1 | μs | 93 |
CAD (KiCad official)
- Symbol:
GD32F470ZKT6 - Footprint:
Package_QFP:LQFP-144_20x20mm_P0.5mm - 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files:
gd32f470zkt6-etched.step/gd32f470zkt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd32f470zkt6.step/gd32f470zkt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (121 pp, sha256
1d9d1bb7b6ef3092, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).