# GD32F470VET6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F470VET6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant GPIO; default PE2, alternate SPI3_SCK, ENET_MII_TXD3, EXMC_A23, EVENTOUT. |
| 2 | PE3 | bidirectional | 5 V tolerant GPIO; default PE3, alternate EXMC_A19, EVENTOUT. |
| 3 | PE4 | bidirectional | 5 V tolerant GPIO; default PE4, alternate SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT. |
| 4 | PE5 | bidirectional | 5 V tolerant GPIO; default PE5, alternate TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT. |
| 5 | PE6 | bidirectional | 5 V tolerant GPIO; default PE6, alternate TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT. |
| 6 | VBAT | power_in | Backup domain supply pin; default function VBAT, no voltage limit given in this excerpt. |
| 7 | PC13-TAMPER-RTC | bidirectional | 5 V tolerant GPIO; default PC13, alternate EVENTOUT, additional RTC_TAMP0, RTC_OUT, RTC_TS. |
| 8 | PC14-OSC32IN | bidirectional | 5 V tolerant GPIO; default PC14, additional function OSC32IN (low-speed crystal input). |
| 9 | PC15-OSC32OUT | bidirectional | 5 V tolerant GPIO; default PC15, additional function OSC32OUT (low-speed crystal output). |
| 10 | VSS | power_in | Digital ground pin; default function VSS. |
| 11 | VDD | power_in | Digital supply pin; default function VDD. |
| 12 | PH0 | bidirectional | 5 V tolerant GPIO; default PH0, additional function OSCIN (high-speed oscillator input). |
| 13 | PH1 | bidirectional | 5 V tolerant GPIO; default PH1, additional function OSCOUT (high-speed oscillator output). |
| 14 | NRST | input | Reset pin; default function NRST, with NRST pin characteristics given in section 4.11. |
| 15 | PC0 | bidirectional | 5 V tolerant GPIO; default PC0, alternate USBHS_ULPI_STP, EVENTOUT, additional ADC012_IN10. |
| 16 | PC1 | bidirectional | 5 V tolerant GPIO; default PC1, alternate SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ENET_MDC, EVENTOUT, additional ADC012_IN11. |
| 17 | PC2 | bidirectional | 5 V tolerant GPIO; default PC2, alternate SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ENET_MII_TXD2, EVENTOUT, additional ADC012_IN12. |
| 18 | PC3 | bidirectional | 5 V tolerant GPIO; default PC3, alternate SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ENET_MII_TX_CLK, EVENTOUT, additional ADC012_IN13. |
| 19 | VDD | power_in | Digital supply pin; default function VDD. |
| 20 | VSSA | power_in | Analog ground pin; default function VSSA. |
| 21 | VREFP | power_in | Positive reference voltage pin; default function VREF+. |
| 22 | VDDA | power_in | Analog supply pin; default function VDDA. |
| 23 | PA0-WKUP | bidirectional | 5 V tolerant GPIO; default PA0, alternate TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ENET_MII_CRS, EVENTOUT, additional ADC012_IN0 and WKUP. |
| 24 | PA1 | bidirectional | 5 V tolerant GPIO; default PA1, alternate TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX, ENET_MII_RX_CLK, ENET_RMII_REF_CLK, EVENTOUT, additional ADC012_IN1. |
| 25 | PA2 | bidirectional | 5 V tolerant GPIO; default PA2, alternate TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ENET_MDIO, EVENTOUT, additional ADC012_IN2. |
| 26 | PA3 | bidirectional | 5 V tolerant GPIO; default PA3, alternate TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, ENET_MII_COL, TLI_B5, EVENTOUT, additional ADC012_IN3. |
| 27 | VSS | power_in | Digital ground pin; default function VSS. |
| 28 | VDD | power_in | Digital supply pin; default function VDD. |
| 29 | PA4 | bidirectional | GPIO; default PA4, alternate SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, TLI_VSYNC, EVENTOUT, additional ADC01_IN4 and DAC_OUT0. |
| 30 | PA5 | bidirectional | GPIO; default PA5, alternate TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT, additional ADC01_IN5 and DAC_OUT1. |
| 31 | PA6 | bidirectional | 5 V tolerant GPIO; default PA6, alternate TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2, EVENTOUT, additional ADC01_IN6. |
| 32 | PA7 | bidirectional | 5 V tolerant GPIO; default PA7, alternate TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, ENET_MII_RX_DV, ENET_RMII_CRS_DV, EVENTOUT, additional ADC01_IN7. |
| 33 | PC4 | bidirectional | 5 V tolerant GPIO; default PC4, alternate ENET_MII_RXD0, ENET_RMII_RXD0, EVENTOUT, additional ADC01_IN14. |
| 34 | PC5 | bidirectional | 5 V tolerant GPIO; default PC5, alternate USART2_RX, ENET_MII_RXD1, ENET_RMII_RXD1, EVENTOUT, additional ADC01_IN15. |
| 35 | PB0 | bidirectional | 5 V tolerant GPIO; default PB0, alternate TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1, ENET_MII_RXD2, SDIO_D1, EVENTOUT, additional ADC01_IN8 and IREF. |
| 36 | PB1 | bidirectional | 5 V tolerant GPIO; default PB1, alternate TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ENET_MII_RXD3, SDIO_D2, EVENTOUT, additional ADC01_IN9. |
| 37 | PB2 | bidirectional | 5 V tolerant GPIO; default PB2 with BOOT1 function, alternate TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT. |
| 38 | PE7 | bidirectional | 5 V tolerant GPIO; default PE7, alternate TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT. |
| 39 | PE8 | bidirectional | 5 V tolerant GPIO; default PE8, alternate TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT. |
| 40 | PE9 | bidirectional | 5 V tolerant GPIO; default PE9, alternate TIMER0_CH0, EXMC_D6, EVENTOUT. |
| 41 | PE10 | bidirectional | 5 V tolerant GPIO; default PE10, alternate TIMER0_CH1_ON, EXMC_D7, EVENTOUT. |
| 42 | PE11 | bidirectional | 5 V tolerant GPIO; default PE11, alternate TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3, EVENTOUT. |
| 43 | PE12 | bidirectional | 5 V tolerant GPIO; default PE12, alternate TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4, EVENTOUT. |
| 44 | PE13 | bidirectional | 5 V tolerant GPIO; default PE13, alternate TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE, EVENTOUT. |
| 45 | PE14 | bidirectional | 5 V tolerant GPIO; default PE14, alternate TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11, TLI_PIXCLK, EVENTOUT. |
| 46 | PE15 | bidirectional | 5 V tolerant GPIO; default PE15, alternate TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT. |
| 47 | PB10 | bidirectional | 5 V tolerant GPIO; default PB10, alternate TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, ENET_MII_RX_ER, SDIO_D7, TLI_G4, EVENTOUT. |
| 48 | PB11 | bidirectional | 5 V tolerant GPIO; default PB11, alternate TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, ENET_MII_TX_EN, ENET_RMII_TX_EN, TLI_G5, EVENTOUT. |
| 49 | NC | unconnected | Not connected pin as printed in the pin table. |
| 50 | VDD | power_in | Digital supply pin; default function VDD. |
| 51 | PB12 | bidirectional | 5 V tolerant GPIO; default PB12, alternate TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ENET_MII_TXD0, ENET_RMII_TXD0, USBHS_ID, EVENTOUT. |
| 52 | PB13 | bidirectional | 5 V tolerant GPIO; default PB13, alternate TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ENET_MII_TXD1, ENET_RMII_TXD1, EVENTOUT, I2C1_TXFRAME, additional USBHS_VBUS. |
| 53 | PB14 | bidirectional | 5 V tolerant GPIO; default PB14, alternate TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT. |
| 54 | PB15 | bidirectional | 5 V tolerant GPIO; default PB15, alternate RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT. |
| 55 | PD8 | bidirectional | 5 V tolerant GPIO; default PD8, alternate USART2_TX, EXMC_D13, EVENTOUT. |
| 56 | PD9 | bidirectional | 5 V tolerant GPIO; default PD9, alternate USART2_RX, EXMC_D14, EVENTOUT. |
| 57 | PD10 | bidirectional | 5 V tolerant GPIO; default PD10, alternate USART2_CK, EXMC_D15, TLI_B3, EVENTOUT. |
| 58 | PD11 | bidirectional | 5 V tolerant GPIO; default PD11, alternate USART2_CTS, EXMC_A16/EXMC_CLE, EVENTOUT. |
| 59 | PD12 | bidirectional | 5 V tolerant GPIO; default PD12, alternate TIMER3_CH0, USART2_RTS, EXMC_A17/EXMC_ALE, EVENTOUT. |
| 60 | PD13 | bidirectional | 5 V tolerant GPIO; default PD13, alternate TIMER3_CH1, EXMC_A18, EVENTOUT. |
| 61 | PD14 | bidirectional | 5 V tolerant GPIO; default PD14, alternate TIMER3_CH2, EXMC_D0, EVENTOUT. |
| 62 | PD15 | bidirectional | 5 V tolerant GPIO; default PD15, alternate TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC. |
| 63 | PC6 | bidirectional | 5 V tolerant GPIO; default PC6, alternate TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT. |
| 64 | PC7 | bidirectional | 5 V tolerant GPIO; default PC7, alternate TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT. |
| 65 | PC8 | bidirectional | 5 V tolerant GPIO; default PC8, alternate TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT. |
| 66 | PC9 | bidirectional | 5 V tolerant GPIO; default PC9, alternate CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT. |
| 67 | PA8 | bidirectional | 5 V tolerant GPIO; default PA8, alternate CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC. |
| 68 | PA9 | bidirectional | 5 V tolerant GPIO; default PA9, alternate TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT, additional USBFS_VBUS. |
| 69 | PA10 | bidirectional | 5 V tolerant GPIO; default PA10, alternate TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME. |
| 70 | PA11 | bidirectional | 5 V tolerant GPIO; default PA11, alternate TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT. |
| 71 | PA12 | bidirectional | 5 V tolerant GPIO; default PA12, alternate TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT. |
| 72 | PA13 | bidirectional | 5 V tolerant GPIO; default JTMS/SWDIO function, also PA13, alternate EVENTOUT. |
| 73 | NC | unconnected | Not connected pin as printed in the pin table. |
| 74 | VSS | power_in | Digital ground pin; default function VSS. |
| 75 | VDD | power_in | Digital supply pin; default function VDD. |
| 76 | PA14 | bidirectional | 5 V tolerant GPIO; default JTCK/SWCLK function, also PA14, alternate EVENTOUT. |
| 77 | PA15 | bidirectional | 5 V tolerant GPIO; default JTDI function, also PA15, alternate TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT. |
| 78 | PC10 | bidirectional | 5 V tolerant GPIO; default PC10, alternate SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, TLI_R2, EVENTOUT. |
| 79 | PC11 | bidirectional | 5 V tolerant GPIO; default PC11, alternate I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT. |
| 80 | PC12 | bidirectional | 5 V tolerant GPIO; default PC12, alternate I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT. |
| 81 | PD0 | bidirectional | 5 V tolerant GPIO; default PD0, alternate SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT. |
| 82 | PD1 | bidirectional | 5 V tolerant GPIO; default PD1, alternate SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT. |
| 83 | PD2 | bidirectional | 5 V tolerant GPIO; default PD2, alternate TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT. |
| 84 | PD3 | bidirectional | 5 V tolerant GPIO; default PD3, alternate SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT. |
| 85 | PD4 | bidirectional | 5 V tolerant GPIO; default PD4, alternate USART1_RTS, EXMC_NOE, EVENTOUT. |
| 86 | PD5 | bidirectional | 5 V tolerant GPIO; default PD5, alternate USART1_TX, EXMC_NWE, EVENTOUT. |
| 87 | PD6 | bidirectional | 5 V tolerant GPIO; default PD6, alternate SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT. |
| 88 | PD7 | bidirectional | 5 V tolerant GPIO; default PD7, alternate USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT. |
| 89 | PB3 | bidirectional | 5 V tolerant GPIO; default JTDO/PB3 function, alternate TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT. |
| 90 | PB4 | bidirectional | 5 V tolerant GPIO; default JNTRST/PB4 function, alternate TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME. |
| 91 | PB5 | bidirectional | 5 V tolerant GPIO; default PB5, alternate TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ENET_PPS_OUT, DCI_D10, EVENTOUT. |
| 92 | PB6 | bidirectional | 5 V tolerant GPIO; default PB6, alternate TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT. |
| 93 | PB7 | bidirectional | 5 V tolerant GPIO; default PB7, alternate TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL/EXMC_NADV, DCI_VSYNC, EVENTOUT. |
| 94 | BOOT0 | input | Boot mode selection pin; default function BOOT0, listed as I/O 5 V tolerant in the table. |
| 95 | PB8 | bidirectional | 5 V tolerant GPIO; default PB8, alternate TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, SPI4_MOSI, CAN0_RX, ENET_MII_TXD3, SDIO_D4, DCI_D6, TLI_B6, EVENTOUT. |
| 96 | PB9 | bidirectional | 5 V tolerant GPIO; default PB9, alternate TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7, EVENTOUT. |
| 97 | PE0 | bidirectional | 5 V tolerant GPIO; default PE0, alternate TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT. |
| 98 | PE1 | bidirectional | 5 V tolerant GPIO; default PE1, alternate TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT. |
| 99 | VSS | power_in | Digital ground pin; default function VSS. |
| 100 | VDD | power_in | Digital supply pin; default function VDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on other I/O | VIN |  |  | 3.6 | V |  | 72 |
| Maximum current for GPIO pins | IIO | -25 |  | 25 | mA |  | 72 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 72 |
| Power dissipation at TA = 85°C of LQFP100 | PD |  |  | 697 | mW | TA = 85°C | 72 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 72 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 72 |
| Variations between different VDD power pins | /ΔVDDX/ |  |  | 50 | mV |  | 72 |
| Variations between different ground pins | /VSSX −VSS/ |  |  | 50 | mV |  | 72 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 72 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 72 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 72 |
| AHB clock frequency | fHCLK |  |  | 240 | MHz |  | 73 |
| APB1 clock frequency | fAPB1 |  |  | 60 | MHz |  | 73 |
| APB2 clock frequency | fAPB2 |  |  | 120 | MHz |  | 73 |
| VDD rise time rate | tVDD | 0 |  |  | μs/V |  | 73 |
| VDD fall time rate |  | 20 |  |  | μs/V |  | 73 |
| Electrostatic discharge voltage (human body model) | VESD(HBM) |  |  | 5000 | V | TA = 25 °C; JS-001-2017 | 83 |
| Electrostatic discharge voltage (charge device model) | VESD(CDM) |  |  | 1000 | V | TA = 25 °C; JS-002-2018 | 83 |
| Static latch-up I-test | LU I-test | -200 |  | 200 | mA | TA = 105 °C; JESD78 | 83 |
| Vsupply over voltage |  |  |  | 5.4 | V |  | 83 |
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 25 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 83 |
| Recommended matching capacitance on OSCIN and OSCOUT | CHXTAL |  | 20 | 30 | pF |  | 83 |
| Crystal or ceramic duty cycle (HXTAL) | Ducy(HXTAL) | 30 | 50 | 70 | % |  | 83 |
| External clock source or oscillator frequency (HXTAL bypass) | fHXTAL_ext | 1 |  | 50 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 84 |
| OSCIN high or low time (HXTAL bypass) | tH/L(HXTAL) | 5 |  |  | ns |  | 84 |
| OSCIN rise or fall time (HXTAL bypass) | tR/F(HXTAL) |  |  | 10 | ns |  | 84 |
| Duty cycle (HXTAL bypass) | Ducy(HXTAL) | 40 |  | 60 | % |  | 84 |
| Crystal or ceramic duty cycle (LXTAL) | Ducy(LXTAL) | 30 |  | 70 | % |  | 85 |
| External clock source or oscillator frequency (LXTAL bypass) | fLXTAL_ext |  | 32.768 | 1000 | kHz | VDD = 3.3 V | 85 |
| OSC32IN high or low time (LXTAL bypass) | tH/L(LXTAL) | 450 |  |  | ns |  | 85 |
| OSC32IN rise or fall time (LXTAL bypass) | tR/F(LXTAL) |  |  | 50 | ns |  | 85 |
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1.73 |  | 1.1 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 86 |
| IRC16M oscillator frequency accuracy, factory-trimmed | ACCIRC16M | -1 |  | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 86 |
| IRC16M oscillator duty cycle | DucyIRC16M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 86 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -1.31 |  | 0.39 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 86 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -2 |  | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 86 |
| IRC48M oscillator duty cycle | DIRC48M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 86 |
| PLL input clock frequency | fPLLIN | 1 |  | 4 | MHz |  | 87 |
| PLL output clock frequency | fPLLOUT | 100 |  | 500 | MHz |  | 87 |
| PLL VCO output clock frequency | fVCO | 32 |  | 344 | MHz |  | 87 |
| PLL lock time | tLOCK |  |  | 400 | μs |  | 87 |
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 50 |  |  | kcycles | TA = -40 °C ~ +85 °C | 89 |
| Word programming time | tPROG |  | 37.5 | 180 | μs | TA = -40°C ~ +85°C | 89 |
| Sector(16kB) erase time | tERASE16kB |  | 200 | 2000 | ms | TA = -40°C ~ +85°C | 89 |
| Sector(64kB) erase time | tERASE64kB |  | 300 | 4000 | ms |  | 89 |
| Mass erase time (512K flash) | tMERASE(512K) |  | 2.4 | 32 | s | TA = -40°C ~ +85°C | 89 |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL |  |  | 0.11 | V | IO_Speed:level 3; IIO = +8 mA; VDD = 2.6 V | 90 |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL |  |  | 0.1 | V | IO_Speed:level 3; IIO = +8 mA; VDD = 3.3 V | 90 |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL |  |  | 0.29 | V | IO_Speed:level 3; IIO = +20 mA; VDD = 2.6 V | 90 |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL |  |  | 0.27 | V | IO_Speed:level 3; IIO = +20 mA; VDD = 3.3 V | 90 |
| Low level output voltage for an IO Pin (IO_Speed level 3) | VOL |  |  | 0.26 | V | IO_Speed:level 3; IIO = +20 mA; VDD = 3.6 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 2.46 |  |  | V | IO_Speed:level 3; IIO = +8 mA; VDD = 2.6 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 3.18 |  |  | V | IO_Speed:level 3; IIO = +8 mA; VDD = 3.3 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 3.48 |  |  | V | IO_Speed:level 3; IIO = +8 mA; VDD = 3.6 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 2.22 |  |  | V | IO_Speed:level 3; IIO = +20 mA; VDD = 2.6 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 2.98 |  |  | V | IO_Speed:level 3; IIO = +20 mA; VDD = 3.3 V | 90 |
| High level output voltage for an IO Pin (IO_Speed level 3) | VOH | 3.29 |  |  | V | IO_Speed:level 3; IIO = +20 mA; VDD = 3.6 V | 91 |
| Thermal resistance, junction-to-ambient (LQFP100) | θJA |  | 57.42 |  | °C/W | Natural convection, 2S2P PCB | 117 |
| Thermal resistance, junction-to-case (LQFP100) | θJC |  | 13.85 |  | °C/W | Cold plate, 2S2P PCB | 118 |

## CAD (KiCad official)

- Symbol: `GD32F470VET6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `gd32f470vet6-etched.step` / `gd32f470vet6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f470vet6.step` / `gd32f470vet6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835986571333632) (121 pp, sha256 `d41c6034187c17e2`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f470vet6-datasheet.pdf)